Takeo Ikezawa

Atomistic 3D process/device simulation considering gate line-edge roughness and poly-Si random crystal orientation effects [MOSFETs]

Using newly developed simulation tools for the precise design of sub-100 nm MOSFETs, intrinsic statistical fluctuations in device characteristics were examined. Ion implantation and subsequent dopant diffusion/activation were simulated based on Monte Carlo procedures. 3D device simulations were performed based on the conventional drift-diffusion model in which electrostatic potential distributions were constructed from the long-range Coulombic components of individual discrete dopant atom potentials. Gate line-edge-roughness (LER) and random discrete dopant effects were incorporated in this simulation. Another possible source of fluctuation, i.e. gate poly-Si crystalline grain random orientation effects in conjunction with oblique halo implantation, was also examined. An atomistic approach to both 3D process and device simulations enabled us to closely examine the coupling effects of the significant sources of fluctuation, i.e. LER and random-discrete-dopant, in the context of practical fabrication processes.

Effects of Selecting Channel Direction in Improving Performance of Sub-100 nm MOSFETs Fabricated on (110) Surface Si Substrate

We investigated the low field mobility and short channel characteristics of metal-oxide-semiconductor field-effect transistors (MOSFETs) on (110) surface Si substrates with various channel directions from the viewpoints of experiment and numerical simulation. We found that the mobility (µ) ratio of (110) substrates to (001) substrates (µ(110)/µ(001)) does not depend on the vertical electric field due to the identical surface roughness for (110) and (001) substrates. We verified mobility enhancement and its channel direction dependence by conducting a detailed carrier transport simulation using a full band model and relaxation time approximation. We obtained good threshold voltage (Vth) lowering characteristics due to the suppression of channeling at the source and drain (SD) extension by implant sequence control. Our results showed that the improvement in propagation delay time (CV/I) and on-current ratio of nMOS to pMOS (Ionn/Ionp) obtained by using an optimized combination of channel directions and a (110) surface Si substrate is attractive for future LSIs down to the sub-100 nm region.

Investigation of realistic dopant fluctuation induced device characteristics variation for sub-100 nm CMOS by using atomistic 3D process/device simulator

We have investigated device characteristics fluctuations of deep sub-100 nm CMOS devices induced by the statistical nature of the number and position of discrete dopant atoms by using newly developed three dimensional atomistic device simulator coupled with realistic atomistic process simulator. The gate length dependence of threshold voltage and drain current fluctuations for both p- and n-MOSFETs has been calculated. Coupling of the atomistic process and device simulations enables us to perform sensitivity analysis of the threshold voltage fluctuation in terms of independent dopant contribution, such as that of the dopant in the source/drain or channel region.

3D MOSFET simulation considering long-range Coulomb potential effects for analyzing statistical dopant-induced fluctuations associated with atomistic process simulator

We have developed a realistic 3-D process/device simulation method for investigating the fluctuation in device characteristics induced by the statistical nature of the number and position of discrete dopant atoms. We used it to investigate the variations in characteristics of a sub-100 nm CMOS device induced by realistic dopant fluctuations considering practical device fabrication processes. In particular, sensitivity analysis of the threshold voltage fluctuation was performed in terms of the independent dopant contribution, such as that of the dopant in the source/drain region or channel region.

Coupled atomistic 3D process/device simulation considering both line-edge roughness and random-discrete-dopant effects

We developed new simulation tools for the precise design of sub-100nm MOSFETs. The intrinsic statistical nature of these devices is expressed as fluctuations in device characteristics. Line-edge-roughness (LER) is incorporated in the structural variations in polysilicon gate masks for halo and source/drain-extensions implantations. The statistical nature of these discrete dopant distributions can be automatically included in the simulation by using Monte Carlo procedures for ion implantation and dopant diffusion/activation processes with different computationally generated LER patterns for each individual device. Our 3D device simulations were based on the classical drift-diffusion approach in which electrostatic potentials are constructed from the long-range Coulombic components of individual dopant atom potentials. Using a 3D atomistic approach to both process and device simulation enabled us to closely examine the coupling effects of the most significant sources of fluctuation, i.e. line-edge-roughness and random-discrete-dopants in the context of practical fabrication processes.

Dopant diffusion model refinement and its impact on the calculation of reverse short channel effect

A couple of dopant diffusion models were examined and refined in terms of both diffusion profiles and simulation of device characteristics. The refinement included appropriate binding-energy values for dopant-defect pairs, electrical activation for arsenic, and the boundary condition for the interstitial-silicon. These are directly related to the quantitative simulation of the reverse short-channel effect (RSCE) for initially flat channel profile nMOSFETs. Source/drain implantation damage is the most crucial factor for the RSCE. For LDD devices, the calculation assuming a certain mid-range value for the coefficient representing the ratio of damage to arsenic dosage reproduced the measured threshold voltage rising quite well.

Improved sub-10-nm CMOS devices with elevated source/drain extensions by tunneling si-selective-epitaxial-growth

Improved sub-10-nm CMOS devices have been investigated by the elevated source/drain extensions (eSDE) using the tunneling silicon selective epitaxial growth (Si-SEG) in the reverse-order source/drain formation. In this eSDE technology, the SEG-Si thickness for eSDE region is precisely controlled by the self-limited Si-SEG process within a narrow slit underneath a SiN sidewall film. Moreover, the SEG-Si film for the elevated source/drain (eS/D) region is also achieved simultaneously. As the results of simultaneously-reduced short-channel effect and parasitic resistance, the Ioff-CV/I characteristics are remarkably improved for both n- and pMOSFETs, as compared with published sub-10-nm planar bulk CMOS devices

Simulation of high-temperature millisecond annealing-based on atomistic modeling of boron diffusion/activation in silicon

An advanced annealing technique.where high temperature is applied for a ~ f ewm illiseconds was investigated through an atomistic process simulation program. In this basic study into the feasibility of this new annealing technique, our aim was to clarify what is happening under the ideal conceptual condition of high-temperature millisecond annealing.

Aggressive design of millisecond annealing junctions for near-scaling-limit bulk CMOS using raised source/drain extensions

An aggressive junction design concept is proposed for further scaling of bulk CMOS featuring selective epi-growth raised source/drain extentions (RSDext) in conjunction with high temperature millisecond annealing (MSA) process. The junction design window enlarged by introducing the RSDext enables us to perform elaborate control of slight ldquointentionalrdquo diffusion onto the MSA process rather than aiming complete--diffusion-less junctions. Such the ldquoeffectiverdquo ultra-shallow junctions under the raised S/D-extentions are demonstrated, in this paper, to exhibit both lower parasitic resistance and lower junction leakage while maintaining superior short-channel-effect suppression, i.e. VTH roll-off characteristics, and any reliability issues.

Sub-30nm Mosfet Fabrication Technology Incorporating Precise Dopant Profile Design using Diffusion-Less High-Activation Laser Annealing

Sub-30nm MOSFET fabrication technology is proposed based on a dedicated process redesign suitable for a non-melt laser annealing technique. Two major features of the laser annealing (LA), i.e. diffusion-less and higher dopant activation enable us to apply more elaborate channel engineering, involving multiple halo implantations and optimized gate-predoping, that contributes further scaling of a functional gate-length (Lg) and effective gate-insulator thickness (Tinv), maintaining sufficient current drivability prior to any local stress engineering applied, for instance, ION = 650/340 [muA/mum] (nMOS/pMOS) at IOFF = 100 nA/mum, Vdd = 0.9V, were obtained for sub-30nm Lg (and also sidewall length) devices