Masami Hane

A 0.063 µm 2 FinFET SRAM cell demonstration with conventional lithography using a novel integration scheme with aggressively scaled fin and gate pitch

We demonstrate the smallest FinFET SRAM cell size of 0.063 µm2 reported to date using optical lithography. The cell is fabricated with contacted gate pitch (CPP) scaled to 80 nm and fin pitch scaled to 40 nm for the first time using a state-of-the-art 300 mm tool set. A unique patterning scheme featuring double-expose, double-etch (DE2) sidewall image transfer (SIT) process is used for fin formation. This scheme also forms differential fin pitch in the SRAM cells, where epitaxial films are used to merge only the tight pitch devices. The epitaxial films are also used for conformal doping of the devices, which reduces the external resistance significantly. Other features include gate-first metal gate stacks and transistors with 25 nm gate lengths with excellent short channel control.

Ultra-thin-body and BOX (UTBB) fully depleted (FD) device integration for 22nm node and beyond

We present UTBB devices with a gate length (L<inf>G</inf>) of 25nm and competitive drive currents. The process flow features conventional gate-first high-k/metal and raised source/drains (RSD). Back bias (V<inf>bb</inf>) enables V<inf>t</inf> modulation of more than 125mV with a V<inf>bb</inf> of 0.9V and BOX thickness of 12nm. This demonstrates the importance and viability of the UTBB structure for multi-V<inf>t</inf> and power management applications. We explore the impact of GP, BOX thickness and V<inf>bb</inf> on local V<inf>t</inf> variability for the first time. Excellent A<inf>Vt</inf> of 1.27 mV·µm is achieved. We also present simulations results that suggest UTBB has improved scalability, reduced gate leakage (I<inf>g</inf>) and lower external resistance (R<inf>ext</inf>), thanks to a thicker inversion gate dielectric (T<inf>inv</inf>) and body (T<inf>si</inf>) thickness.

Statistical Compact Model Parameter Extraction by Direct Fitting to Variations

In this paper, a new method of statistical compact model parameter extraction is proposed and described in detail. The method is characterized in that the target of fitting is not the individual transistor, but statistically analyzed results (more specifically, principal components) of measured data. Variations of transistor characteristics can be translated into equivalent variations of compact model parameters by only one fitting step without repeating the parameter extraction procedure multiple times. Since the fitting is based on the response of a compact model to parameters, detailed information of the model is not necessary. The method has been applied to modeling the variations of metal-oxide-semiconductor field-effect transistor current versus voltage characteristics, and its validity has been confirmed.

Effects of Selecting Channel Direction in Improving Performance of Sub-100 nm MOSFETs Fabricated on (110) Surface Si Substrate

We investigated the low field mobility and short channel characteristics of metal-oxide-semiconductor field-effect transistors (MOSFETs) on (110) surface Si substrates with various channel directions from the viewpoints of experiment and numerical simulation. We found that the mobility (µ) ratio of (110) substrates to (001) substrates (µ(110)/µ(001)) does not depend on the vertical electric field due to the identical surface roughness for (110) and (001) substrates. We verified mobility enhancement and its channel direction dependence by conducting a detailed carrier transport simulation using a full band model and relaxation time approximation. We obtained good threshold voltage (Vth) lowering characteristics due to the suppression of channeling at the source and drain (SD) extension by implant sequence control. Our results showed that the improvement in propagation delay time (CV/I) and on-current ratio of nMOS to pMOS (Ionn/Ionp) obtained by using an optimized combination of channel directions and a (110) surface Si substrate is attractive for future LSIs down to the sub-100 nm region.

Investigation of realistic dopant fluctuation induced device characteristics variation for sub-100 nm CMOS by using atomistic 3D process/device simulator

We have investigated device characteristics fluctuations of deep sub-100 nm CMOS devices induced by the statistical nature of the number and position of discrete dopant atoms by using newly developed three dimensional atomistic device simulator coupled with realistic atomistic process simulator. The gate length dependence of threshold voltage and drain current fluctuations for both p- and n-MOSFETs has been calculated. Coupling of the atomistic process and device simulations enables us to perform sensitivity analysis of the threshold voltage fluctuation in terms of independent dopant contribution, such as that of the dopant in the source/drain or channel region.

Highly reliable BEOL-transistor with oxygen-controlled InGaZnO and Gate/Drain offset design for high/low voltage bridging I/O operations

Reliability of BEOL-transistors with a wide-gap oxide semiconductor InGaZnO (IGZO) film, integrated on LSI Cu-interconnects, is intensively discussed in terms of application to on-chip bridging I/Os between low and high voltage interactive operations (Fig. 1). Oxygen control in the thin IGZO film was found to be important to stabilize the device characteristics. A conventional IGZO tends to contain deep-level donor-states, which cause temperature and bias instabilities. The oxygen control in IGZO reduces these deep donor-states to improve operation instability. A gate/drain offset structure effectively suppresses the hot-carrier generation, resulting in a stable operation at high Vd bias condition (∼20V). The oxygen-controlled IGZO and gate/drain offset structure are important for making the BEOL-transistors applicable to high/low voltage I/Os bridging.

Operation of functional circuit elements using BEOL-transistor with InGaZnO channel for on-chip high/low voltage bridging I/Os and high-current switches

Functional circuit elements based on novel BEOL-transistors with a wide-band-gap oxide semiconductor InGaZnO (IGZO) film are integrated onto LSI Cu-interconnects, and their operations are demonstrated. High-current comb-type transistors show excellent Ion/Ioff ratio (>;108) and high-Vd operation with linear area dependence, realizing area-saving compact high-current BEOL switches. Successful operation of voltage-controlled inverter switches with high-Vd enables on-chip bridging I/Os between high/low voltage on conventional Si system LSIs. Setting the gate-to-drain offset design to just 0.1μm realizes +20V enhancement of the breakdown voltage to ~60V with excellent safety operation at around Vd=50V due to the wide-band-gap characteristics.

Effects of drain bias on threshold voltage fluctuation and its impact on circuit characteristics

Enhancement mechanism of Vth fluctuation in saturation region is analyzed through addressable transistor array measurement and 3D Monte-Carlo TCAD simulation. It was confirmed that random dopant fluctuation (RDF) in heavily doped halo devices enhances source-drain asymmetry, resulting in non-Gaussian distributions of DIBL and saturation Vth (Vth_sat). The measured DIBL behavior was accurately modeled and implemented in statistical circuit simulation, to evaluate the impact on SRAM stability. Optimization of halo for mitigating RDF is important for achieving aggressively scaled SRAM cells.

Electron holography for analysis of deep submicron devices: Present status and challenges

A potential distribution analysis of source/drain (SD) regions in sub-30-nm-gate-length metal-oxide-semiconductor field-effect transistors (MOSFETs) is presented as an example of the present status of electron holography analysis. First, the authors describe experimental setups that determine the resolutions of the analysis in practice. They show that specimen preparation artifacts significantly affect the energy resolution and that the artifacts can be reduced by preparing specimens using low-energy back side ion milling. Second, they describe the SD potential analysis in sub-30-nm-gate-length MOSFETs.

Synthetic soft error rate simulation considering neutron-induced single event transient from transistor to LSI-chip level

Soft error phenomena induced by the Sea-level cosmic neutron have been investigated by using a simulation system that covers from an individual MOSFET device level to an LSI-chip level. This system consists of the several kinds of simulation codes/tools, such as a mixed-mode 3D device simulator, SPICE circuit simulator, and analyzing tools of gate-level net-lists. A comprehensive practical simulation flow is demonstrated in this paper on commercial 90 nm generation logic devices and standard-cells.