Kazuya Uejima

Electron holography for analysis of deep submicron devices: Present status and challenges

A potential distribution analysis of source/drain (SD) regions in sub-30-nm-gate-length metal-oxide-semiconductor field-effect transistors (MOSFETs) is presented as an example of the present status of electron holography analysis. First, the authors describe experimental setups that determine the resolutions of the analysis in practice. They show that specimen preparation artifacts significantly affect the energy resolution and that the artifacts can be reduced by preparing specimens using low-energy back side ion milling. Second, they describe the SD potential analysis in sub-30-nm-gate-length MOSFETs.

Electron holography analysis of a shallow junction for planar-bulk metal-oxide-semiconductor field-effect transistors approaching the scaling limit

We investigated electrostatic potential distributions in source∕drain extensions (SDEs) in metal-oxide-semiconductor field-effect transistors (MOSFETs) fabricated using state-of-the-art junction formation technology. We first demonstrate that electron holography can directly reveal potential distribution in scaled MOSFETs when specimen preparation artifacts are reduced, which we did by using back side low-energy Ar ion milling. Second, we examine the potential distributions in SDEs in a scaled (30‐nm-gate-length) MOSFET fabricated by using a combination of cluster B implantation, millisecond annealing, and multihalo implantation. The results show that these junction formation technologies enable fabrication of very abrupt and shallow (10‐nm-deep) SDE junctions. In addition, our experimental analysis, in conjunction with a Monte Carlo doping-process simulation, indicates that B channeling along the ⟨110⟩ direction of the Si substrate during the implantation process significantly blurs the SD junction profi...

Highly Efficient Stress Transfer Techniques in Dual Stress Liner CMOS Integration

Double disposable sidewall spacers (DDSW) process and adhesion reinforcement technique (ART) are proposed, for the first time, demonstrating efficient stress-transfer from the dual stress liner (DSL) to the FET channel region. A thin L-shape sidewall formed by the DDSW process was designed to compensate decreased channel stress resulted from the aggressive pitch scaling. A +10% enhancement of channel conductance has been achieved for NTETs by the DDSW process compared with a conventional DSL one. For PFETs, achieved +23% Ion enhancement by using the ART, was resulted from avoiding stress degradation in the DSL process and optimizing the DSL layout.

Pushing Planar Bulk CMOSFET Scaling to its Limit by Ultimately Shallow Diffusion-Less Junction

The scaling limit of planar bulk MOSFETs with ultra-shallow junction (USJ) by using diffusion-less high-activation annealing technique has been investigated. Incorporation of cluster-ion (B18H22) implantation for PFETs and high-temperature msec-annealing, where the dedicated fabrication-process was redesigned including multiple halo implantation and thin SD-silicidation, enables us to examine near-scaling limit bulk CMOS device performance with ultimately shallow junction (5-15 nm). Techniques developed here to overcome trade-off between the functionable minimum gate length (Lmin) and on-current (Ion, including suppression of surface-recess on S/D extension, higher activation of S/D-extension with optimized msec-annealing condition and the resistance reduction with optimized spacing of the bottleneck at the joint of S/D-ext and deep-S/D junction. Those techniques highly contribute device performance enhancement by effectively reducing large parasitic resistance due to extremely shallow Xj. Theoretical estimation implies that fully low parasitic resistance, thin Tinv and ultimately shallow Xj extend Lmin scaling to about 20 nm for planar bulk CMOSFET.

Aggressive design of millisecond annealing junctions for near-scaling-limit bulk CMOS using raised source/drain extensions

An aggressive junction design concept is proposed for further scaling of bulk CMOS featuring selective epi-growth raised source/drain extentions (RSDext) in conjunction with high temperature millisecond annealing (MSA) process. The junction design window enlarged by introducing the RSDext enables us to perform elaborate control of slight ldquointentionalrdquo diffusion onto the MSA process rather than aiming complete--diffusion-less junctions. Such the ldquoeffectiverdquo ultra-shallow junctions under the raised S/D-extentions are demonstrated, in this paper, to exhibit both lower parasitic resistance and lower junction leakage while maintaining superior short-channel-effect suppression, i.e. VTH roll-off characteristics, and any reliability issues.

Sub-30nm Mosfet Fabrication Technology Incorporating Precise Dopant Profile Design using Diffusion-Less High-Activation Laser Annealing

Sub-30nm MOSFET fabrication technology is proposed based on a dedicated process redesign suitable for a non-melt laser annealing technique. Two major features of the laser annealing (LA), i.e. diffusion-less and higher dopant activation enable us to apply more elaborate channel engineering, involving multiple halo implantations and optimized gate-predoping, that contributes further scaling of a functional gate-length (Lg) and effective gate-insulator thickness (Tinv), maintaining sufficient current drivability prior to any local stress engineering applied, for instance, ION = 650/340 [muA/mum] (nMOS/pMOS) at IOFF = 100 nA/mum, Vdd = 0.9V, were obtained for sub-30nm Lg (and also sidewall length) devices

Novel diffusion-less ultra-shallow junction engineering based on millisecond annealing for sub-30 nm gate length planar bulk CMOSFET

The formation of ultra-shallow junction (USJ) less than 10 nm by using diffusion-less high-activation millisecond annealing technique has been investigated for deeply scaled planar bulk CMOS. This achievement relies on cross-sectional visualization of impurity distributions in MOSFET based on the electron beam holography technology with extremely high spatial resolution. Incorporation of cluster-ion (B18H22) implantation for PFETs and high-temperature millisecond-annealing, where the dedicated fabrication-process was redesigned including multiple halo implantation and thin S/D-silicidation, enables us to examine near-scaling limit bulk CMOS device performance with ultimately shallow junction. Furthermore, the parasitic resistance reduction with optimized spacing of the bottleneck at the joint of S/D-extension and deep-S/D junction was developed to overcome trade-off between the functionable minimum gate length (Lmin) and on-current (Ion) of MOSFET. Those techniques that realize fully low parasitic resistance and ultimately shallow xj extend Lmin scaling to less than 30 nm for planar bulk CMOS devices.

Parasitic resistance and leakage reduction by raised source / drain extention fabricated with cluster ion implantation and millisecond annealing

We designed and fabricated sub-30 nm gate length pMOSFETs developing the raised source/drain extension (RSDext) process. Our process features usages of cluster-ion (B18H22) implantation and high-temperature millisecond annealing processes and a facet-structure-control of the RSDext of less than 10 nm thickness for suppressing a fringe capacitance increase for the “effective” ultra-shallower junction formation. As the results, experimentally obtained our pMOSFETs with raised source/drain extension show almost the same LMIN, 1/2 times lower parasitic resistance and lower junction leakage.

Electron Holography Characterization of Shallow Junction Fabricated By Diffusion‐less Process for Sub‐30 nm Gate‐Length MOSFETs

Cross‐sectional electron holography was used for two‐dimensional potential mapping of source/drain extensions (SDEs) in scaled MOSFETs fabricated using state‐of‐the‐art junction formation technology. First, we show that specimen‐preparation artifacts, which have prevented detailed examinations of scaled SDEs, are significantly reduced by using low‐energy backside Ar+ milling. Next, we demonstrate that electron holography clearly reveals very shallow (10‐nm‐deep) SDE junction profiles. We also show that the experimental examinations, in conjunction with doping‐process simulations, allow examinations of how dopant distribution, such as junction depth and abruptness, affect the potential distribution in planar‐bulk MOSFETs approaching the scaling limit.

Novel polycrystalline gate engineering for high performance sub-100 nm CMOS devices

We have developed a design for a polycrystalline (poly-) gate to be used in high performance sub-100 nm CMOS devices. The inversion capacitance (C/sub inv/) in a device with poly-gate was found to obviously decrease as the gate length becomes shorter in the range below 100 nm (C/sub inv/ lowering). The explanation for this C/sub inv/ lowering is as follows: (1) the gate length becoming shorter than the poly-grain size (R/sub G/) and (2) the short dopant-diffusion length from grain boundaries (D/sub H/). Techniques for achieving small values for R/sub G/ and large values for D/sub H/ improved the I/sub D/ figures by +15% for the pFET and by +3% for the nFET that have poly-SiGe gates with L/sub G/=65 nm.