Takashi Uchino

A raised source/drain technology using in-situ P-doped SiGe and B-doped Si for 0.1-/spl mu/m CMOS ULSIs

An advanced CMOS design, where a raised source/drain and contact windows are formed over the field oxide is realized by using P-doped SiGe and B-doped Si selective epitaxial growth techniques. Excellent short-channel characteristics and reduced parasitic drain junction capacitance were obtained. NMOS and PMOSFETs with an effective channel length of 0.12 /spl mu/m and ultra-shallow junctions with a depth of 25 nm were fabricated. These devices had a low extension resistance of about 370 /spl Omega//sq.

A 64 GHz Si bipolar transistor using in-situ phosphorus doped polysilicon emitter technology

A high-performance bipolar transistor technology has been developed for emitter formation using in-situ phosphorus doped polysilicon (IDP). Using this technology, a Si bipolar transistor was designed with a shallow emitter junction, an ultra-high current gain, and a cutoff frequency (f/sub T/) of 64 GHz. Furthermore, the product of f/sub T/ and BV ceo of 200 GHz-V has been achieved. This value is nearly equal to the physical limitation for homojunction silicon transistors. The technology reported here is believed to be very promising for future fabrication of ultra-high-speed high-density bipolar and BiCMOS VLSIs.<<ETX>>

In situ phosphorus-doped polysilicon emitter technology for very high-speed, small emitter bipolar transistors

In situ phosphorus-doped polysilicon emitter (IDP) technology for very high-speed, small-emitter bipolar transistors is studied. The device characteristics of IDP transistors are evaluated and compared with those of conventional ion-implanted polysilicon emitter transistors. IDP technology is used to fabricate double polysilicon self-aligned bipolar transistors and the I-V characteristics, current gain, transconductance, emitter resistance, and cut-off frequency are measured. In conventional transistors, these device characteristics degrade when the emitter is small because of the emitter-peripheral-thick-polysilicon effect. In IDP transistors, the peripheral effect is completely suppressed and large-grain, high-mobility polysilicon can be used. The device characteristics, therefore, are not degraded in sub-0.2-/spl mu/m emitter transistors. In addition, large-grain, high-mobility, and high phosphorus concentration IDP films increase current gain and lower emitter resistance. The use of IDP technology to build very small emitter transistors is evaluated and discussed.

Very-high-speed silicon bipolar transistors with in-situ doped polysilicon emitter and rapid vapor-phase doping base

We present a detailed study of the performance of very-high-speed silicon bipolar transistors with ultra-shallow junctions formed by thermal diffusion. Devices are fabricated with double-polysilicon self-aligned bipolar technology with U-groove isolation on directly bonded SOI wafers to reduce the parasitic capacitances. Very thin and low resistivity bases are obtained by rapid vapor-phase doping (RVD), which is a vapor diffusion technique using a source gas of B/sub 2/H/sub 6/. Very shallow emitters are formed by in-situ phosphorus doped polysilicon (IDP) emitter technology with rapid thermal annealing (RTA). In IDP emitter technology, the emitters are formed by diffusion from the in-situ phosphorus doped amorphous silicon layer. Fabricated transistors are found to have ideal I-V characteristics, large current gain and low emitter resistance for a small emitter. Furthermore, a minimum ECL gate delay time of 15 ps is achieved using these key techniques. Analyses of the high performance using circuit and device simulations indicate that the most effective delay components of an ECL gate are cut-off frequency and base resistance. A high cut-off frequency is achieved by reducing the base width and active collector region. In this study, RVD is used to achieve both high cut-off frequency and low base resistance at the same time. >

MOSFETs with ultrashallow junction and minimum drain area formed by using solid-phase diffusion from SiGe

An advanced CMOS structure, in which a raised source/drain and contact windows formed over the field oxide, was fabricated. Ultrashallow junction formation using solid-phase diffusion from doped SiGe layers was used to fabricate MOSFETs. These MOSFETs demonstrated excellent short-channel characteristics and 70%-80%-reduced parasitic drain-junction capacitance. They have ultrashallow junctions with a depth of 25 nm and a low source/drain extension (SDE) resistance: 350 /spl Omega//sq (NMOSFETs) and 390 /spl Omega//sq (PMOSFETs). The isotropic diffused SDE structure was formed by using solid-phase diffusion, which could effectively form a shallow junction and a suitable overlap between gate and SDE. This structure results in good short-channel characteristics and high current drivability.

A 64-GHz f/sub T/ and 3.6-V BV/sub CEO/ Si bipolar transistor using in situ phosphorus-doped and large-grained polysilicon emitter contacts

A high-performance bipolar transistor has been developed using an in-situ phosphorus doped polysilicon (IDP) technique for emitter formation. The transistor demonstrated in ultrahigh current gain of 700, a maximum cutoff frequency f/sub T(max)/ of 64 GHz, and a breakdown voltage between collector and emitter BV/sub CEO/ of 3.6 V. At V/sub CE/ values of 2 and 3 V, a product of f/sub T(max)/ and BV/sub CEO/ of 200 GHz-V has been achieved. This value is nearly equal to the physical limitation for homojunction silicon transistors. >

15-ps ECL/74-GHz f/sub T/ Si bipolar technology

A very high performance Si bipolar transistor technology has been developed. In-situ phosphorus doped polysilicon (IDP) emitter technology was used to reduce the thermal budget and emitter resistance. Very thin bases were obtained by rapid vapor-phase doping (RVD) and low energy BF2/sup +/ ion implantation. Double-polysilicon self-aligned bipolar technology with U-groove isolation on bonded SOI wafers was used to reduce the parasitic capacitances. Using these key techniques, a minimum ECL gate delay time of 15 ps and a cut-off frequency of 74 GHz have been achieved.<<ETX>>

Effect of rapid epitaxy in in situ phosphorus-doped polysilicon emitter on current-gain of bipolar transistors

The effect of rapid solid-phase epitaxy (SPE) on the current gain of in situ phosphorus-doped polysilicon-emitter (IDP) transistors has been evaluated, IDP technology is used to produce very-high-speed small-emitter bipolar transistors, which have very high current gain due to their hetero-emitter-like characteristics. The IDP film is deposited on a clean poly/mono-silicon surface, followed by rapid thermal annealing (RTA). The poly/mono interface was analyzed and the lattice image was observed by high-resolution transmission electron microscopy (TEM). The majority of the IDP transistors had poly/mono-silicon interfacial hetero-emitter-like characteristics and thus had high current gain. The remaining transistors, however, did not exhibit hetero-emitter-like characteristics due to SPE and thus the current gain was reduced. These results are well explained using an interfacial residual-stress model: rapid epitaxy occurs when the amorphous silicon film is annealed by RTA, which eliminates the interfacial residual stress and in turn the hetero-emitter-like characteristics.

0.1 /spl mu/m CMOS with shallow and steep source/drain extensions fabricated by using rapid vapor-phase doping (RVD)

We have developed an advanced 0.1 /spl mu/m CMOS technology to form 39 nm deep p-type junctions with sheet resistance as low as 630 /spl Omega//sq using two techniques in combination: rapid vapor-phase doping (RVD) and solid-phase diffusion (SPD). These RVD- and SPD-devices have shown excellent short channel characteristics down to 0.1 /spl mu/m effective channel length and 40% higher maximum drain current compared with conventional devices with ion implanted source/drain extensions (SDEs), and high-speed circuit performance. We have also investigated the effect of the SDE structure on device performance. We found that a gate-extension overlap of 0.05 /spl mu/m enabled excellent DC and high-speed circuit performance in 0.1-/spl mu/m devices.