Ichiro Ohshima

Tantalum nitride metal gate FD-SOI CMOS FETs using low resistivity self-grown bcc-tantalum layer

A tantalum nitride (TaNx) metal gate complementary metal oxide semiconductor (CMOS) technology using low-resistivity (/spl sim/15 /spl mu//spl Omega/cm), bcc (body-centered-cubic)-phase tantalum metal layer has been developed, featuring low-temperature processing below 550/spl deg/C except for gate oxide formation. It was found for the first time that TaNx works not only as a buffer layer which prevents tantalum metal film and gate oxide film from reacting with each other, but also as a seed layer which helps self-growth of bcc-phase tantalum films by hetero-epitaxy. Furthermore, we have demonstrated that the work function of TaNx gate is close to midgap of silicon, hence similar to titanium nitride (TiNx) gate. We have also demonstrated that MOS capacitors on bulk and fully-depleted silicon-on-insulator (FD-SOI) CMOS with TaNx/bcc-Ta/TaNx stacked metal gate structure have excellent electrical characteristics and that the ring-oscillator fabricated using the stacked metal gate CMOS can be operated successfully with 3.8 nm-thickness gate oxide.

Advantage of silicon nitride gate insulator transistor by using microwave excited high-density plasma for applying 100nm technology node

We have succeeded to prepare a hgh quality silicon nitride gate insulator with lower gate leakage current in three orders of magnitude compared to that of conventional thermal oxide film, by using a Kr/NH3 mixed gas microwave-excited highdensity plasma with metal (TaN/Ta/TaN) gate. Moreover, we have evaluated the current drive capability dependence on the silicon surface orientation and found that the channel hole mobility on (110) surface at the channel-width direction of 13 5 degree from the (111) cut plane was 2.4 times hlgher than that of (100) surface. The CMOS transistor with the silicon nitride gate insulator formed by the microwave-excited plasma and TaN/Ta/TaN metal gate on (110) surface orientation silicon having a higher current drive capability and high integration density is the most practical candidate for lOOnm technology node and beyond.

Chemical reaction concerns of gate metal with gate dielectric in Ta gate MOS devices: an effect of self-sealing barrier configuration interposed between Ta and SiO/sub 2/

Chemical reaction of gate metal with gate dielectric for Ta gate MOS devices has been experimentally investigated both by electrical and physical measurements: capacitance-voltage (C-V), current-voltage (I-V), transmission electron microscopy (TEM), energy dispersive X-ray (EDX), electron diffraction measurements. In spite of the chemical reaction of Ta with SiO/sub 2/ consuming /spl sim/1-nm-thick in gate oxide, the interface trap densities of /spl sim/2/spl times/10/sup 10/ cm/sup -2/ eV/sup -1/ at midgap and ideal channel mobility characteristics have been observed in the Ta gate MOS devices with 5.5-nm-thick thermal oxide gate dielectric. Considering the experimental data with theoretical calculation based on thermodynamics together, a barrier layer model has been developed for the Ta gate MOS systems. The physical mechanism involved is probably self-sealing barrier layer formation resulting from the chemical reaction kinetics in the free-energy change of Ta-Si-O system.

Design and Fabrication of MOS Device Circuits with Reticle-Free Exposure Method

An arbitrary pattern exposure method employing a liquid crystal display (LCD) for the formation of projection images has been applied to the design and fabrication of metal oxide semiconductor (MOS) devices and circuits. In this process, a transparent-type LCD with 1024×768 pixels and a g-line stepper were used. To realize the global pattern alignment on the stepper, we newly arranged an LCD reticle fitting the LCD on a quartz reticle which has a conventional alignment mark suitable for the stepper, in place of a conventional glass reticle. The MOS devices has been newly designed and fabricated with four layers in order to evaluate this new lithography concept. It has been confirmed that the n-MOS device can be correctly fabricated by this concept with reducing the manufacturing time. From the results, it is convinced that this method has the potential for replacing conventional glass reticles, particularly in the trial stage of device development.

Very High Reliability of Ultrathin Silicon Nitride Gate Dielectric Film for sub-100nm Generation

This paper focuses attention on electrical properties of ultra-thin silicon nitride (Si3N4) films directly grown on Si surfaces by microwave-excited high-density plasma system as an alternative gate dielectric. We demonstrated the electrical characteristics of the MNS capacitors with the Si3N4 films. The TDDB lifetime of the MNS capacitor is over 30,000 times larger compared with that of the MOS capacitor with the conventional dry oxide. Furthermore, the hysteresis of C-V curve measured at 400K can not be observed. Introduction The continued scaling of silicon oxide gate dielectrics to the fundamental limits governed by large gate leakage current requires the introduction of higher dielectric constant films, e.g. Si3N4. Furthermore, the higher reliability of gate dielectrics is required for sub-100nm technology nodes [1]. We have succeeded in forming the Si3N4 gate dielectric film by microwave-excited high-density plasma at a low temperature[2]. In the direct nitridation of silicon surface, Kr/NH3 mixed gas was used. Due to the excellent interface characteristics, it is expected as an alternative gate dielectric. In recent research, we found that using Xe/NH3 mixed gas and Xe plasma irradiation before nitridation can improve the reliability dramatically. The purpose of this paper is to investigate electrical properties of improved high reliability Si3N4 gate insulator. Experimental MNS capacitors were fabricated on Cz n-type (100) silicon substrate with a resistivity of 0.5Ω・cm. The Si3N4 films were grown with the process pressure of 50mTorr using Kr/NH3 or Xe/NH3 mixed gas. Some samples have been treated by Xe plasma irradiation of 60sec before the direct nitridation. The microwave frequency is 2.45 GHz and the power was 5 W/cm. A TaNx metal gate electrode was formed by reactive sputtering at room temperature to eliminate gate depletion [3]. Subsequently patterning and wet etching of the gate electrode were performed for gate formation. Post metal annealing was carried out at 400°C in H2/N2=0.2/1.8 SLM for 30 minutes. The high-frequency (1MHz) C-V, J-V and constant voltage (Vg=+3.4V) TDDB characteristics have been investigated in this research. Results and Discussion Fig.1 shows the 50 % TDDB lifetime of the gate dielectric films as a function of the applied gate voltage. The lifetime of MNS capacitor with Kr/NH3 nitridation is 800 times larger than that of MOS capacitor. In our research, it is known that the process pressure of 50mTorr is suitable for the direct nitridation. However, the low pressure is important factor of the higher electron temperature, as shown in Fig.2. Fig.3 shows the scattering cross section as the function of electron temperature [4]. From the figure, it is possible to reduce the electron temperature in the plasma by using the Xe gas instead of the Kr gas, which we used to form Si3N4 films until now. As the results, the electrical properties and the reliability have been improved drastically due to the lower damage in the Si3N4 growth period. Fig.4 shows the weibull plots of constant voltage (Vg=+3.4 V) TDDB measurement for the MNS capacitors with the Si3N4 film grown by the Kr/NH3 (EOT=1.9 nm), the Xe/NH3 (EOT=1.9 nm) and the Xe/NH3 after Xe plasma irradiation (EOT=1.9 nm). The TDDB lifetime of the Si3N4 film grown by Xe/NH3 after Xe plasma irradiation is 40 times larger than that grown by Kr/NH3. This means that the lifetime of the Si3N4 film formed by Xe/NH3 is 30,000 times larger than that of conventional oxide. Fig.5 shows the J-V curves of MNS capacitors. The leakage current of Si3N4 grown by Xe/NH3 after Xe plasma irradiation is reduced to 1/9 of that formed by Kr/NH3 at gate bias of 1 V. In Fig.6, a 20mV hysteresis exists in High frequency (1 MHz) C-V curve of Si3N4 film formed by Kr/NH3 at a raised temperature of 400K. Fig.7 shows that there is no hysteresis existing at the Si3N4 film grown by Xe based direct nitridation. Fig.8 shows the AFM photos of Si substrate with or without 1hour Xe plasma irradiation before direct nitridation. The roughness of Si surface without Xe irradiation (Ref.) is 0.17 nm and that with Xe irradiation is 0.15 nm. The micro-roughness of the Si surface irradiated by the Xe plasma is the same as that of the initial surface. These results indicate that the Xe exited plasma is very effective for the Si3N4 film formation compare with Kr or Ar exited plasma. Conclusion We succeeded in improving the reliability of MNS devices by Xe based process due to the lower damage in the Si3N4 growth period. The TDDB lifetime of Si3N4 gate dielectric film formed by Xe based process is 40 times larger than that grown by Kr/NH3 and 30,000 times larger than that formed by conventional oxide. Furthermore, Xe based process suppresses the hysteresis of C-V curve at the temperature of 400K. This Si3N4 film is sufficient ability for the gate insulator of 65 nm generation. References [1] Chen-Yen Chang et al. Microelectronics Reliability p.553 (1999) [2] K. Sekie, et al. Vac Technol. p. 3129 (1999) [3] H. Shimada, et al.. VLSI Technol. p. 67 (2001) [4] B. Chapman, Glow Discharge Processes, John Wiley & Sons, New York, (1980), Chap.2 Extended Abstracts of the 2003 International Conference on Solid State Devices and Materials, Tokyo, 2003, 452 P3-2 pp. 452-453

Thinning of SOI by numerically controlled Plasma CVM (Chemical Vaporization Machining)-Evaluation of Machined Surface for Electron Devices-

The trial manufacture of the ultra-thin SOI (Silicon on Insulator) wafer has already been carried out by numerically controlled plasma CVM (Chemical Vaporization Machining). In this paper, it is evaluated whether the wafer machined by plasma CVM can use as a substrate for a semiconductor integrated circuit. Though metal contamination and some particles are brought in the machining, it has been confirmed that they are removed by usual wet cleaning after the machining. The characteristic of the MOS diode formed on the machined wafer and the reference wafer is evaluated, and it is shown that both characteristics are equivalent. Furthermore, the ID-VG characteristic of the MOSFET formed on the machined SOI wafer and the reference SOI wafer is compared, and it is shown that both characteristics are also equivalent. That is to say, it has been concluded that the wafer machined by plasma CVM is usable as a substrate for a semiconductor integrated circuit.

Ultra clean process gas recycling system for plasma process using krypton and xenon

Introduction of rare Kr(Xe) gases into ULSI mass production requires the recycling of exhaust gases. We describe a gas pumping system that enables efficient recycling of Kr and Xe gases. A newly developed screw pump is able to exhaust without involving the atmosphere in its exhaust gases. Moreover, this screw pump needs a smaller volume of purge gases to realize clean pumping than conventional dry pumps. A novel bellows pump can compress recycle gases without involving the atmosphere. These pumping systems enable ultra clean process gas recycling system for the plasma process using krypton and xenon.