Cecile Aulnette

Stress Metrology : The challenge for the next generation of engineered wafers

Raman spectroscopy is a powerful and versatile technique for stress measurements in complex stacks of thin crystalline layers at macroscopic and microscopic scales. Using such a technique we show that thick SiGe layers epitaxially grown using graded buffer method are fully relaxed (>95%) at a macroscopic scale but exhibit a small strain modulation at a microscopic scale. For the first time we report the results of Raman micro-mapping of stress distribution in SGOI wafers produced by Smart Cut TM technology. We conclude that Smart Cut TM is a unique method to manufacture the next generation of engineered wafers that can combine strained and/or relaxed SiGe alloys, Si and Ge films, while keeping their initial strain properties at both scales. It is important to develop Raman spectroscopy tool for in-line process control in fabrication of strained Silicon On Insulator (sSOI) wafers.

Overview of FDSOI technology from substrate to device

To meet low power circuit requirements, increased channel mobility is required to boost transistor performance and reduce Vdd for lower power dissipation without performance penalty. SOI and more advanced engineered substrates developed on the SOI platform provide solutions for 32 technology nodes and beyond. The options include process-induced strain, biaxial strain virtual substrates, modification of surface and channel orientation, or selection of channel materials with high mobility and high saturation velocities such as Ge, SiGe alloys, and III/V compound semiconductors. The ultra-thin-body SOI devices with undoped and strained channels can be used to control the SCE and reduce the sub-threshold leakage for scaling and low power dissipation. Such fully depleted devices promise excellent performance, high circuit density at very low power, a critically important attribute for the rapidly growing realm of portable consumer electronics like smart phone and mobile internet device. In addition, SOI enables some unique applications that would be very difficult if not impossible in bulk Si, such as RF devices in high resistivity substrates, ultra-thin RFID chips, backside imagers, MEMS, photonic integrated circuits, and flexible electronics.

SiGe and Ge on Insulator Wafers

Since 90nm technology Germanium (Ge) element has become increasingly popular in the CMOS processing for enhancing transistor performance, especially enhancing hole mobility for P-type transistors. The main driver has been the embedded SiGe in the source/drain region and its extraordinary boost on PFET drive current [1]. More recently Ge has enabled band engineering with respect to Silicon for Vt tuning [2,3] in addition to channel engineering for mobility enhancement. Looking into the future the need for SiGe alloys or pure Ge is increasing, as it is contemplated as a seed for IIIV material growth [4], or even the replacement of Si by Ge in the channel to take advantage of the high electron and hole mobilities [5]. Today the manufacturing reality shows us that all Ge needs can be fulfilled by epitaxy during the processing of the devices [6]. In this paper we will introduce the Dual Channel substrate having a strained SiGe layer grown on top of a SOI substrate. Starting with this wafer and thru condensation process one can produce a uniform SiGe layer suitable for Fully Depleted applications.

Splitting kinetics of Si0.8Ge0.2 layers implanted with H or sequentially with He and H

We have performed systematic measurements of the splitting kinetics induced by H-only and He+H sequential ion implantation into relaxed Si0.8Ge0.2 layers and compared them with the data obtained in Si. For H-only implants, Si splits faster than Si0.8Ge0.2. Sequential ion implantation leads to faster splitting kinetics than H-only in both materials and is faster in Si0.8Ge0.2 than in Si. We have performed secondary ion mass spectrometry, Rutherford backscattering spectroscopy in channeling mode, and transmission electron microscopy analyses to elucidate the physical mechanisms involved in these splitting phenomena. The data are discussed in the framework of a simple phenomenological model in which vacancies play an important role.

Ultra-thin SOI for 20nm node and beyond

Recent UTBB device data at sub-25nm gate length demonstrate good performance, small VT variation and excellent low power operation. In addition, very uniform Soitec Xtreme SOI™ product substrates are now available and compliant with device requirements. Thus the level of maturity of UTBB devices and substrates makes it possible for introduction at 20nm node. Multiple options at the substrate level to further boost the performance open up the path to improve performance for future nodes.

Smart Cut Technology: The Path for Advanced SOI Substrates

In microelectronics, photonics, opto-electronics, high frequency or high power device applications, the needs for specific substrate solutions are more and more required. Smart Cut™ technology appears as the technological answer that enables the industrial to provide engineered substrate solutions tailored to the applications. For instance a large spectrum of SOI type structures are today in volume manufacturing. At present the industrial is focused on composite substrates. This paper focuses on the realization of advanced SOI, strained SOI, SOQ substrates and many other examples of engineered substrates. Highlights are given on the most recent developments.