Takeshi Miyaba

A CMOS bandgap reference circuit with sub-1-V operation

This paper proposes a CMOS bandgap reference (BGR) circuit, which can successfully operate with sub-1-V supply, In the conventional BGR circuit, the output voltage V/sub ref/ is the sum of the built-in voltage of the diode V/sub f/ and the thermal voltage V/sub T/ of kT/q multiplied by a constant. Therefore, V/sub ref/ is about 1.25 V, which limits a low supply-voltage operation below 1 V. Conversely, in the proposed BGR circuit, V/sub ref/ has been converted from the sum of two currents; one is proportional to V/sub f/ and the other is proportional to V/sub T/. An experimental BGR circuit, which is simply composed of a CMOS op-amp, diodes, and resistors, has been fabricated in a conventional 0.4-/spl mu/m flash memory process. Measured V/sub ref/ is 518/spl plusmn/15 mV (3/spl sigma/) for 23 samples on the same wafer at 27-125/spl deg/C.

A CMOS band-gap reference circuit with sub 1 V operation

This paper proposes a CMOS band-gap reference (BGR) circuit, which can successfully operate with sub-1 V. In the conventional BGR circuit, the output voltage, Vref, is the sum of the built-in voltage of the diode, Vf, and the thermal voltage, VT, of kT/q multiplied by a constant. Thereby, Vref is about 1.25 V, which limits a low Vcc operation below 1 V. Conversely, in the proposed BGR circuit, Vref has been converted from the sum of two currents; one is proportional to Vf; and the other is proportional to VT. An experimental BGR circuit, which is simply composed of a CMOS opamp, diodes, and resistors, has been fabricated in a conventional double metal 0.4 /spl mu/m process. Measured Vref is 515 mV/spl plusmn/15 mV (3 /spl sigma/) for 23 samples on the same wafer at 27/spl deg/C through 125/spl deg/C.

A channel-erasing 1.8 V-only 32 Mb NOR flash EEPROM with a bit-line direct-sensing scheme

A 1.8 V-only 32 Mb NOR flash EEPROM uses a channel-erasing scheme for the 0.49 /spl mu/m/sup 2/ cell in 0.25 /spl mu/m CMOS technology. The block decoder circuit with an erase-reset sequence performs channel-erase. The bit line direct sense permits sub-1.8 V operation, suitable for use in handheld systems.A 1.8-V-only 32-Mb NOR flash EEPROM has been developed based on the 0.25-/spl mu/m triple-well double-metal CMOS process. A channel-erasing scheme has been implemented to realize a cell size of 0.49 /spl mu/m/sup 2/, the smallest yet reported for 0.25-/spl mu/m CMOS technology. A block decoder circuit with a novel erase-reset sequence has been designed for the channel-erasing operation. A bitline direct sensing scheme and a wordline boosted voltage pooling method have been developed to obtain high-speed reading operation at low voltage. An access time of 90 ns at 1.8 V has been realized.

Wordline voltage generating system for low-power low-voltage flash memories

A low-power wordline voltage generating system is developed for low-voltage flash memories. The limit for the stand-by current including the operation current for the band-gap reference and the stand-by wordline voltage generator is discussed. The system was implemented on a 1.8-V 32-Mb flash memory fabricated with a 0.25-/spl mu/m flash memory process and achieved with very low stand-by current of 2 /spl mu/A typically, and high operating frequency of 25 MHz in read operation at 1.8 V. A low-voltage level shifter with high-speed switching is also proposed.

A 44-mm/sup 2/ four-bank eight-word page-read 64-Mb flash memory with flexible block redundancy and fast accurate word-line voltage controller

Combining a negative-gate channel-erasing NOR flash memory technology with an aggressively-scaled NAND flash process technology results in a 64 Mb NOR flash memory with 0.27 /spl mu/m/sup 2/ cell and 44 mm/sup 2/ chip. The flash memory provides 4 independent banks for flexible dual operation and unique block redundancy for yield.

A 3.3 V-only 16 Mb flash memory with row-decoding scheme

A 3.3 V only 16 M flash memory with a row decoding scheme is fabricated in 0.4 /spl mu/m double-well double-metal CMOS. Negative-gate-biased erase enables 3.3 V-only operation, and a double-word-line structure with second aluminum minimizes word-line delay. Row redundancy with self-convergence improves yield. Quasi-differential sensing with address transition detection gives fast random access.

A 2.9mW, +/− 85ppm accuracy reference clock generator based on RC oscillator with on-chip temperature calibration

A novel on-chip frequency calibration of temperature dependency is proposed for CMOS reference frequency generator. High-order temperature coefficients are rapidly extracted by employing a carefully designed on-chip heater, so that the frequency deviation due to the temperature variation is accurately estimated, and compensated in digitally by means of all-digital PLL (ADPLL). The proposed technique was implemented in a 0.18um CMOS and achieved ±85ppm accuracy at 24MHz, consuming a power of 2.9mW.

A 187.5µVrms-read-noise 51mW 1.4Mpixel CMOS image sensor with PMOSCAP column CDS and 10b self-differential offset-cancelled pipeline SAR-ADC

Low-power and small-area implementations are essential in the mobile-phone market. Serial signal-processing architectures, in which signal-processing circuits such as a programmable-gain amplifier (PGA) and an ADC can be shared by column-level correlated double sampling (CDS) circuits, promise to reduce chip size and power consumption. However, conventional column CDS circuits composed of linear capacitors or NMOS capacitors (NMOSCAPs) with output buffers (OBUFs) still occupy a large footprint. In this work, to reduce the area and the power consumption of column CDS circuits while keeping high linearity, 1.5V PMOS capacitors (PMOSCAPs) are employed. These capacitors work as low-cost sample-and-hold (S/H) capacitors as well as voltage level-shifters by using body-terminal control. To reduce the power consumption of the ADC, instead of a conventional pipeline ADC, we propose a 10b self-differential offset-cancelled pipeline SAR-ADC. It operates with the reference voltage of the ADCs half full-scale voltage (Vfs), leading to a reduction of 80% switching power and 50% capacitor DAC (CDAC) area in the ADC. A black-level correction function is built in the ADC without any additional DACs. The proof-of-concept circuits are implemented in a 1.4Mpixel CMOS image sensor that consumes 51.0mW with a frame rate of 17fps and a read noise of 187.5μVrms at 8.1× analog gain.

A sampling weak-program method to tighten Vth-distribution of 0.5 V for low-voltage flash memories

Recently, it has become increasingly important to lower the supply voltage of fast access time NOR flash EEPROMs for a low power handheld digital equipment. In order to scale the boosted word-line voltage for reading memory data with low power supply, it is necessary to tighten the erased-Vth distribution. The self-convergence method has been proposed to tighten the Vth-distribution within 2 V. However, its not available to tighten the width below 1 V due to the high power consumption and long converging time. Therefore, the bit-by-bit weak program after over-erase-verify is needed. This paper shows a problem of the bit-by-bit weak program and proposes a sampling method of weak program for a solution, which can achieve 0.5 V in the Vth-distribution width, resulting in lowering the word-line voltage for less than 1.5 V operation.