Takeshi Shima

Neuro chips with on-chip back-propagation and/or Hebbian learning

A layered neural net realized with two chips is described. One chip implements 24*24 synapses, a local weight control mechanism, and quantized +or-1 LSB, both momentum and weight update schemes. The other contains 24 neurons, implementing not only backward propagation (BP) but Hebbian learning, with 200-pF drive capability. Some experimental chip characteristics verifying the implemented techniques are given. >

Three-dimensional table look-up MOSFET model for precise circuit simulation

MOSFET models for circuit simulation program are generally required to have a good accuracy and short computation time. The authors have developed a novel table look-up MOSFET model which meets both requirements.

Principle and applications of an autocharge-compensated sample and hold circuit

This paper describes an autocharge-compensated sample and hold circuit (ACC-SH) for thin film transistor active matrix liquid-crystal displays (TFT-AM-LCDs, TFT-LCDs, or LCDs). The operating principle and actual application problems for TFT-LCDs are also discussed. The applicability of the ACC-SH is verified not only by circuit simulation but also by experimental circuit die measurement. >

Neuro chips with on-chip backprop and/or Hebbian learning

In a neural network, neurons and synapses are two unit functions. If the learning procedures are assigned appropriately, they can be placed in tiling form. This arrangement is potentially expandable if constructed of two separate LSI chips, a synapse chip and a neuron chip. The authors describe such an implementation. A single synapse configuration is shown along with a synapse group with 64 synapses and a learning control circuit. A single neuron functional block diagram is presented, and synapse characteristics are shown.<<ETX>>

TFT-LCD panel driver IC using dynamic function shuffling technique

Most of the power supplied to a thin-film transistor liquid crystal display (TFT-LCD) panel is consumed at the video signal input lines of the driver ICs, and at the panel vertical lines driven by the driver ICs. The signal frequency at the video signal inputs is about 240 MHz/spl divide/ (number of lines) and about 60 kHz at the vertical lines assuming a super extended graphics array (SXGA) display format. The parasitic capacitance of each line is over 60 pF on the video input side and over 150 pF at the vertical lines. The required signal amplitude at the vertical lines, which depends on the liquid crystal material, is always more than 3 V/sub pp/ for good black and white picture contrast. Conversely, a small signal amplitude is crucial to low power consumption and low electromagnetic radiation. Thus, a gain stage is needed to amplify the signals. For reasons of signal processing speed, the sample and hold (SH) stage precedes the gain stage. However, this configuration increases the offset pedestal originating from the SH stage at the gain stage. To overcome this, dynamic function shuffling is introduced in this CMOS driver IC.

Low Output-Offset Variation S/H Circuits for An LCD Segment Driver IC Achieving Wide Signal Frequency Bandwidth

The similarities between blood platelets and serotonin (5HT) neurons offer a reliable tool of exploring 5HT system. The aim of our study was to evaluate platelet [3H]imipramine binding in suicide attempters, as compared with depressed patients and healthy controls. In addition, we measured aggressive features in the 3 groups, by a standardized rating scale, the Inventory for assessing different kinds of ostility (QTA). The results showed a significant decrease in the maximum binding capacity (Bmax) of 3H-imipramine binding to platelet membranes in suicide attempters, who also exhibited higher total and single item scores at QTA than healthy controls or depressed patients. Both biological and psychological findings are suggestive of an aggression dysregulation in suicide attempters.

A circuit simulator based on the waveform-relaxation method using selective overlapped partition and classified latencies

Several techniques for improving simulation costs in the waveform relaxation method are discussed. In the circuit partitioner field, selective overlapped partition and duplication depth ideas are proposed. For the circuit simulation part, several modifications to the conventional simulator are demonstrated and classified latencies proposed. Experimental simulations are compared with results obtained from SPICE2. The results indicate conclusively that, if the circuit size is over one thousand, SUPER-SPICE is more cost-effective than SPICE2.<<ETX>>

An autocharge-compensated S/H circuit for TFT-LCD panel

Liquid-crystal displays (LCDs) have been widely used in TV and computer terminals. This article 1 shows a configuration of an LCD module composed of an LCD panel, signal segmentation ICs (SSICs) and a scanning-line controller. One horizontal video signal line, segmented and held in massive parallel S/H circuits in the SSICs, is transferred to a line of pixels through TFTs. The requirements for such a S/H are as follows: 1) sample time, determined by (horizontal scanning time)/(number of horizontal pixels), 2) 5 V full-scale operation range to control LC transparency, 3) over 30 MHz signal bandwidth, 4) low output offset standard deviation both within a chip and between chips, and 5) simple configuration.<<ETX>>