Yukio Kamatani

Neuro chips with on-chip back-propagation and/or Hebbian learning

A layered neural net realized with two chips is described. One chip implements 24*24 synapses, a local weight control mechanism, and quantized +or-1 LSB, both momentum and weight update schemes. The other contains 24 neurons, implementing not only backward propagation (BP) but Hebbian learning, with 200-pF drive capability. Some experimental chip characteristics verifying the implemented techniques are given. >

A 5 Gb/s 8/spl times/8 ATM switch element CMOS LSI supporting five quality-of-service classes with 200 MHz LVDS interface

The switch element (SE) is a 622Mb/s, 8/spl times/8 shared-buffer ATM switch LSI for backbone LAN and WAN applications. The SE has 5 Gbps bandwidth, supporting 5 QoS classes delay priority and link-by-link multicast. Up to a 32/spl times/32 switch with 20 Gbps bandwidth can be configured using multiple SEs and distributor/arbiter (DA) LSIs.

Neuro chips with on-chip backprop and/or Hebbian learning

In a neural network, neurons and synapses are two unit functions. If the learning procedures are assigned appropriately, they can be placed in tiling form. This arrangement is potentially expandable if constructed of two separate LSI chips, a synapse chip and a neuron chip. The authors describe such an implementation. A single synapse configuration is shown along with a synapse group with 64 synapses and a learning control circuit. A single neuron functional block diagram is presented, and synapse characteristics are shown.<<ETX>>

A circuit simulator based on the waveform-relaxation method using selective overlapped partition and classified latencies

Several techniques for improving simulation costs in the waveform relaxation method are discussed. In the circuit partitioner field, selective overlapped partition and duplication depth ideas are proposed. For the circuit simulation part, several modifications to the conventional simulator are demonstrated and classified latencies proposed. Experimental simulations are compared with results obtained from SPICE2. The results indicate conclusively that, if the circuit size is over one thousand, SUPER-SPICE is more cost-effective than SPICE2.<<ETX>>