Tomohisa Kimura

Neuro chips with on-chip back-propagation and/or Hebbian learning

A layered neural net realized with two chips is described. One chip implements 24*24 synapses, a local weight control mechanism, and quantized +or-1 LSB, both momentum and weight update schemes. The other contains 24 neurons, implementing not only backward propagation (BP) but Hebbian learning, with 200-pF drive capability. Some experimental chip characteristics verifying the implemented techniques are given. >

Neuro chips with on-chip backprop and/or Hebbian learning

In a neural network, neurons and synapses are two unit functions. If the learning procedures are assigned appropriately, they can be placed in tiling form. This arrangement is potentially expandable if constructed of two separate LSI chips, a synapse chip and a neuron chip. The authors describe such an implementation. A single synapse configuration is shown along with a synapse group with 64 synapses and a learning control circuit. A single neuron functional block diagram is presented, and synapse characteristics are shown.<<ETX>>

P-32: Mesopic Bit-Depth Analysis for High-Quality TV beyond 10-Bits

A mesopic bit-depth analysis is proposed, which shows HVS-characteristics between subtense angle and bit-depth. It gives a guideline to investigate further cost-down of 11 bits-depth display drivers: rapidly decreasing HVS-characteristics suggests an 8bits-based 4×4 dithering is applicable even for mesopic vision which is more sensible thanphotopic vision.