Taku Ogura

A 1.8-V 256-Mb Multilevel Cell NOR Flash Memory With BGO Function

This paper describes a 1.8-V-only 256-Mb four-level-cell (2 b/cell) NOR flash memory with background operation (BGO) function fabricated in a 130-nm CMOS self-aligned shallow trench isolation (SA-STI) process technology. The new memory array architecture is adopted in which the flash source is connected by local interconnect to reduce the source resistance and constrain the floating-gate coupling effect. The mirrored current sensing read architecture for multilevel-cell operation at a supply voltage of 1.8 V has realized a fast asynchronous random access time (67 ns) and burst read at 54 MHz. A high speed and high reliability of program/erase cycling (100 k) has been achieved by dual-step pulse program algorithm and optimized erase sequence. Page program time and block erase time are 1.54 ms/2 kb and 538 ms/1 Mb, respectively

Compact modeling of a flash memory cell including substrate-bias-dependent hot-electron gate current

We propose a compact model for a Flash memory cell that is suitable for circuit simulation. The model includes a hot-electron gate current model that considers not only channel hot electron injection but also channel initiated secondary electron injection to express properly substrate bias dependence of gate current. Tunneling gate current for erasing is expressed by the BSIM4 tunneling gate current model. Good agreement between measured and simulated results of both programming and erasing characteristics for 130-nm technology Flash memory cells indicates that our model is useful in designing and optimizing circuit for Flash memories.

A 58-nm 2-Gb MLC “B4-Flash” Memory with Flexible Multisector Architecture

A 58-nm 2-Gb multi-level cell (MLC) B4-Flash memory with flexible multisector architecture has been developed, which can be realized by unique features of B4-Flash with P-channel cell; large-data programming with small cell current thanks to back bias-assisted band-to-band tunneling-induced hot electron (B4-HE) injection mechanism, simple erase sequence without over-erase problem. In this architecture, each program and erase unit size can be extended from 256 B to 4 KB and from 256 KB to 4 MB, respectively, by utilizing 8 sectors & 2 banks simultaneous operation, and consequently 10 times faster 3.7 MB/s rewrite speed than that of conventional NOR flash can be realized by 4 KB / 980

Byte alterable embedded EEPROM with B4-HE architecture achieving 10usec programming and 57F2 cell size

\mu \text{s}

Semiconductor memory device having data protection feature

programming and 4 MB / 80 ms erasing. A fast 110-ns random access with enough read margin has been achieved by simultaneous parallel sensing at 3 op-amps with cell-bias compensation scheme. This paper proves that B4-Flash can be a candidate for various applications which need both fast rewrite speed and fast random access as a fast rewritable NOR-type flash with MLC capability and scalability.

CHARGE PUMP CIRCUIT ALLOWING EFFICIENT ELECTRIC CHARGE TRANSFER

This paper describes a byte alterable EEPROM with B4-HE (Back-Bias assisted Band-to-Band tunneling Hot-Electron injection) architecture employing three-transistor of AND-type unit cell for disturb-free operation. B4-EEPROM cell array has been fabricated using a 90 nm flash process, and single-pulse program and erasure cycling has been confirmed up to one million, with keeping programming time of 10 us and erase time of 1 ms. It is demonstrated that the excellent capability of more than 10 years data retention at 150 C. In addition, a fully designed 90 nm B4-EEPROM macro specification has been investigated, and the unit cell size can be designed 57F2, which is a half those of conventional EEPROM cell size of 80-100F2.