Masaaki Mihara

A 288-kb fully parallel content addressable memory using a stacked-capacitor cell structure

A 288-kb (8 K words*36 b) fully parallel content addressable memory (CAM) LSI using a compact dynamic CAM cell with a stacked-capacitor structure and a novel hierarchical priority encoder is described. The stacked-capacitor structure results in a very compact dynamic CAM cell (66 mu m/sup 2/) which is operationally stable. The novel hierarchical priority encoder reduces the circuit area and power dissipation. In addition, a new priority decision circuit is introduced. The chip size is 10.3 mm*12.0 mm using a 0.8- mu m CMOS process technology. A typical search cycle time of 150 ns and a maximum power dissipation of 1.1 W have been obtained using circuit simulation. In fabricated CAM chips, the authors have verified the performance of a search operation at a 170-ns cycle and have achieved a typical read/write cycle time of 120 ns. >

Negative heap pump for low voltage operation flash memory

A negative heap pump circuit which is free from the threshold voltage restriction has been described. The proposed charge pump which heaps up the coupling capacitor must be a key technology for low power operative flash memories.

A 29-mm/sup 2/, 1.8-V-only, 16-Mb DINOR flash memory with gate-protected-poly-diode (GPPD) charge pump

1.8 V-only 16 Mb CMOS divided-bit line-NOR (DINOR) flash memory with alternating background-operation (BGO) capability has 72 ns random access time. The EGO feature allows program or erase in one bank while the device simultaneously allows read in the other bank. This BGO feature is suitable for mobile and personal computing, and communication products. This memory is fabricated using a 0.25 /spl mu/m-design-rule, triple-layer-metal, triplewell CMOS. The cell is 0.80/spl times/0.85 /spl mu/m/sup 2/ and the chip is 4.93/spl times/5.88 mm/sup 2/.

A 288-kbit fully parallel content addressable memory using stacked capacitor cell structure

The authors describe a 288-kb (8 K words*36-b) fully parallel CAM (content addressable memory) LSI using a compact dynamic CAM cell (66 mu m/sup 2/) with stacked capacitor structure and a novel hierarchical priority encoder. The chip size is 10.3*12.0 mm/sup 2/, and the typical cycle time is 150 ns using circuit simulation. This CAM LSI performs large-scale search operations very efficiently, and therefore has the possibility of broad applications to high-performance artificial-intelligence machines and relational database systems.<<ETX>>

Row-redundancy scheme for high-density flash memory

Flash memory is recognized as one of the key devices of personal digital assistant and other portable equipment. Rapid expansion of the market is expected because it is estimated that the cost of flash memory will eventually be lower than that of DRAM. However, to achieve low cost, a highly efficient redundancy scheme must be implemented for the chip. Although the same column redundancy scheme used in DRAM and SRAM can be applied to flash memory, conventional row redundancy in which defective word lines are replaced by spare word lines is not suitable. In flash memory, all memory cells in the erase block must be programmed before the erase pulse is applied to the memory array to avoid over-erasure. If the replaced word line is shorted to the adjacent word line, memory cells on the defective word line cannot be programmed even if the replaced word line is selected because the word line is grounded through the adjacent word line.<<ETX>>