Daisuke Ohshima

A novel ultra-thin package for embedded high-pin-count LSI supported by Cu plate

We have developed a thin, low-thermal-resistance LSI package by embedding a high-pin-count LSI chip into ultra-thin build-up layers supported by Cu plate. The embedded LSI chip is a microprocessor with approximately 1500 pads and a thickness of 50 µm, and it is completely laminated by the first build-up epoxy resin. The total package thickness is only 0.71 mm including a 0.5-mm-thick Cu plate for cooling, which is much thinner than the conventional flip chip ball grid array (FCBGA) package with a heat sink. Our package shows excellent warpage characteristics, smaller than 82 µm in the temperature range from −55 to +260 °C. Low thermal resistance of 10.8 °C/W is achieved at a wind velocity of 0 m/s, which is also comparable to that of the FCBGA with a large heat sink. We have successfully demonstrated the functions of this package using an LSI tester and personal-computer-like system board. It has also passed a 600-cycle package-level thermal cycle test.

Electrical design and demonstration of an embedded high-pin-count LSI chip package

Design techniques for an ultra-thin LSI package embedding a high-pin-count LSI chip in the thin package substrate have been developed to achieve the excellent electrical performance, as well as low warpage and high heat removal. The embedded chip package we designed is 27 mm by 27 mm in size and 0.71 mm in thickness with a heat spreader. The package is attained with only three metal layers against the six metal layers of the product flip chip ball grid array (FCBGA) package using the same chip. Although the two power plane layers have been removed from the substrate, the low impedance of the power distribution network (PDN) is achieved by utilizing many bundles of fine vias. A 0.5-mm-thick copper plate attached to the LSI chips backside provides the signal return path, and contributes to the flatness of this thin package. It also effectively removes heat from the chip. Our design for a product LSI chip with approximately 1,500 pins demonstrates excellent electrical performance as well as small thickness, low warpage, and a high rate of heat removal. Function tests using an LSI tester and a PC-like system board successfully demonstrate the outstanding performance of the LSI chip.

Embedded Active Packaging Technology for High-Pin-Count LSI With Cu Plate

We have developed a thin, reliable, low-thermal-resistance LSI packaging technology by embedding a high-pin-count LSI chip into thin build-up layers supported by Cu plate. The embedded LSI chip is a microprocessor with approximately 1500 pads and a thickness of 50 μm, and it is completely laminated by the first build-up epoxy resin. The total package thickness is only 0.71 mm including a 0.5-mm-thick Cu plate for cooling, which is much thinner than the conventional flip chip ball grid array (FCBGA) package with a heat sink. Our package shows excellent warpage characteristics of only 34 μm at room temperature for 27 × 27 mm2 in size. It is also possible to reduce the total package thickness to 0.46 mm by etching the Cu plate to half thickness, with keeping the warpage increase up to 117 μm. Low thermal resistance of 10.8°C/W is achieved for the packages with 0.5-mm-thick Cu plate at a wind velocity of 0 m/s, which is almost comparable to that of an FCBGA with a large heat sink. We have successfully demonstrated the functions of our packages using an LSI tester and personal-computer-like system board. They have also passed a 1000-cycle package-level thermal cycle test.

Reliability of thin seamless package with embedded high-pin-count LSI chip

We have previously reported the technology for embedding a 1500-pin microprocessor chip in a thin LSI package using a rigid Cu plate. The reliabilities of this seamless package with the direct interconnection between the LSI chip and substrate wiring have now been evaluated at the package and board levels. The package passed all the LSI function tests at the package level even after 2000 thermal cycles. The microstructure of the interconnect, evaluated using electron backscatter diffraction and transmission electron microscopy, showed a high interconnect reliability. The reliability at the board level was evaluated using the thermal cycles testing, the shadow-moiré method and strain gauge measurement with the package mounted on a system board. Thanks to the Cu plate, the warpage and strain characteristics are excellent, resulting in uniform stress distribution. Therefore, this seamless packaging technology is promising for the fabrication of thin, highly reliable LSI packages for replacing flip chip ball grid array packages.

Chip-level and package-level seamless interconnect technologies for advanced packaging

Package-process-oriented thick-Cu-wiring technologies have been developed for forming chip-level and package-level seamless interconnects between an LSI chip and the package substrate. Chip-level seamless interconnects are formed using a resin CMP process. Package-level seamless interconnects are formed by embedding a thinned chip into a resin on Cu base plate. A package with package-level seamless interconnects is thinner and has lower thermal resistance, better power delivery, and finer-pitch interconnects than a conventional flip-chip ball grid array package.

Electrical Design and Techniques for an Embedded High-Pin-Count LSI Chip Package

In order to achieve the excellent electrical performance, as well as low warpage and high heat removal, electrical design techniques for an ultrathin large-scale integration (LSI) package embedding a high-pin-count LSI chip in the thin package substrate have been developed. The embedded chip package we designed is 27 mm × 27 mm in size and 0.71 mm in thickness with a heat spreader. The package is attained with only three metal layers against the six metal layers of the product flip-chip ball grid array package using the same chip, even though the package size is the same. Although the two power plane layers have been removed from the substrate, the low impedance of the power distribution network is achieved by utilizing many bundles of fine vias. A 0.5-mm-thick Cu plate attached to the LSI chips backside provides the signal return path, and contributes to the flatness of this thin package. It also effectively removes heat from the chip. In addition, it functioned as a shield component and results in electromagnetic interference suppression. Our design for a fully operative LSI chip with approximately 1500 pins demonstrates excellent electrical performance as well as small thickness, low warpage, and a high rate of heat removal. Function tests using an LSI tester and a PC-like system board successfully demonstrate the outstanding performance of the LSI chip. Finally, the advantage of a heat sink connected to ground plane of the package is discussed. It is found that, for excellent near-field noise suppression effects, the heat sink must be connected to the ground plane.