Tamio Ikehashi

A 130-mm/sup 2/, 256-Mbit NAND flash with shallow trench isolation technology

Higher density flash memories for mass storage are attractive for application in the audio-video field, for example, in digital cameras and for voice recording. A 100 MB Flash records one hour CD-quality music. Improvements in video compression techniques are expected to realize gigabyte flash, enabling movies on silicon in the near future; a development that is expected to lead to rapidly rising demand for high-density flash. Both the low bit cost due to the small cell size and the high program and read performance are important factors for the high density flash. A NAND flash has potential advantages in those respects. Shallow trench isolation (STI) shrinks bit line pitch to 73% of that in the case of conventional LOCOS isolation, enabling 0.29 um/sup 2/ cell 0.25 /spl mu/m design rules. The 129.76 mm/sup 2/ chip is made possible by using NAND type memory cell and STI.

A 125-mm/sup 2/ 1-Gb NAND flash memory with 10-MByte/s program speed

A single 3-V only, 1-Gb NAND flash memory has been successfully developed. The chip has been fabricated using 0.13-/spl mu/m CMOS STI technology. The effective cell size including the select transistors is 0.077 /spl mu/m/sup 2/. To decrease the chip size, a new architecture is introduced. The in-series connected memory cells are increased from 16 to 32. Furthermore, as many as 16 k memory cells are connected to the same wordline. As a result, the chip size is decreased by 15%. A very small die size of 125 mm/sup 2/ and an excellent cell area efficiency of 70% are achieved. As for the performance, a very fast programming and serial read are realized. The highest program throughput ever of 10.6-MByte/s is realized: 1) by quadrupling the page size and 2) by newly introducing a write cache. In addition, the garbage collection is accelerated to 9.4-MByte/s. In addition, the write cache accelerates the serial read operation and a very fast 20-MByte/s read throughput is realized.

An RF MEMS Variable Capacitor with Intelligent Bipolar Actuation

We propose an IBA scheme based on a pull-out detection, which is suitable for implementing in a circuit. The scheme is implemented in a driver IC that is part of a module with an RF MEMS variable capacitor. No failures are observed over 108 cycles at 85degC, which is an accelerated charging condition.

A source-line programming scheme for low voltage operation NAND flash memories

To realize a low-voltage operation NAND flash memory, a new source-line programming scheme has been proposed. This architecture drastically reduces the program disturbance without circuit area, manufacturing cost, program speed, or power consumption overhead. In order to improve the program disturbance characteristics, a high program inhibit voltage is applied to the channel from the source line, as opposed to from the bit line of the conventional scheme. The bit-line swing is decreased to 0.5 V to achieve a lower power consumption. Although the conventional NAND flash memory cannot operate below 2.0 V due to the program disturbance issue, the proposed NAND flash memory shows excellent program disturbance characteristics irrespective of the supply voltage. A very fast programming of 192 /spl mu/s/page and a very low power operation of 22 mW at 1.4 V can be realized in the proposed scheme.

A high power-handling RF MEMS tunable capacitor using quadruple series capacitor structure

This paper presents an RF MEMS tunable capacitor that achieves an excellent power-handling property with relatively low actuation voltage. The tunable capacitor consists of two fixed MIM (Metal-Insulator-Metal) capacitors and two MEMS capacitor elements, all connected in series. This quadruple series capacitor (QSC) structure enables reduction of the actuation voltage without sacrificing the power-handling capability, since the MIM capacitor reduces the RF voltage amplitude applied to the MEMS capacitors. The measured result demonstrates +36dBm hot-switching at 85°C with 21V pull-in voltage.

A Robust RF MEMS Variable Capacitor with Piezoelectric and Electrostatic Actuation

An RF MEMS variable capacitor using hybrid actuation of piezoelectric and electrostatic forces is presented. A surface micromachining process is used to fabricate the device. The piezoelectric actuator, which uses thin film PZT, enables low voltage actuation while the electrostatic actuator realizes large capacitance ratio. The measured capacitance ratio is Cmax/Cmin=14 at 5V. We demonstrate that the hybrid actuation enables to lower the pull-in voltage without changing the pull-out voltage. We also show that the shift of pull-out voltage due to dielectric charging can be reduced drastically at actuation voltages below 10V. In this sense, the hybrid actuation can realize low voltage operation with enhanced robustness for stiction

Low profile double resonance frequency tunable antenna using RF MEMS variable capacitor for digital terrestrial broadcasting reception

It is difficult to realize the built-in antenna for wideband systems, because a frequency bandwidth of the low profile antenna is narrow. A frequency tunable antenna is a technique for wideband characteristics. In this paper a low profile double resonance frequency tunable antenna using MEMS variable capacitors is presented. It has high efficiency over a wide frequency band. Through both resonant portions from 465 to 665 MHz, the efficiency of more than −4 dB and the VSWR of less than 3 are observed in the measurement using the variable capacitor of 0.4–0.9 pF.

Highly reliable and manufacturable in-line wafer-level hermetic packages for RF MEMS variable capacitor

In this paper, we report a thin-film encapsulation technology for wafer-level micro-electro-mechanical systems (MEMS) variable capacitor package. The electrical characteristics of MEMS are adversely affected by moisture. In order to prevent moisture from permeating into a package, the top surface was protected with a plasma-enhanced chemical vapor deposition (PE-CVD) SiN layer. The developed packages become a hybrid thin-film hermetic encapsulation consisting of an internal shell using PE-CVD SiO, a seal layer coating with resin, and an external protective layer formed by PE-CVD SiN. The process is fully compatible with standard low-cost back-end-of-the-line (BEOL) technologies for LSIs as a wafer-level package (WLP). This hybrid structure was very effective for protecting the MEMS device from external moisture. Moreover, the electrode surface area has to be wide, because a wide range of capacities is necessary in MEMS variable capacitors. We have developed a large (1480 × 1080 µm) hermetic thin-film encapsulation as WLP.

A 60 ns access 32 kByte 3-transistor flash for low power embedded applications

In this paper, we present a new memory, 3-transistor flash (3-Tr), which is suited to the embedded application. The memory cell has inherited low power the erase/program characteristic of the NAND flash. The cell size of the 32kByte 3-Tr flash, fabricated in a 0.4um NAND flash technology, is 4.36 /spl mu/m/sup 2/. This is about 1/8 of the EEPROM cell size having the same design rule. We also propose two circuit technologies, a low power sensing scheme and a double stage boosting scheme (DSB). The sense scheme aims to reduce the power of the read operation without degrading access time. DSB, on the other hand, improves the power consumption property of the word line (WL) decoder during the program mode. It is also immune to a decrease of the supply voltage Vdd.

A CMOS embedded RF-MEMS tunable capacitor for multi-band/multi-mode smartphones

This paper reports on 1-chip RF-MEMS tunable capacitor that equips CMOS driver circuit in the underlying layer. A Wafer Level Chip Scale Package (WLCSP) optimized for RF-MEMS is employed to minimize the module size. The MEMS actuation voltage is generated by an Actuation Voltage Generator (AVG). The boost mechanism employed in the AVG enables instant high voltage generation and reduction of the dielectric charging. The measured noise at RF frequencies is less than -120dbm, thanks to a shield metal layer formed between MEMS and CMOS layers. To achieve high power handing and high creep immunity, we employ the previously reported techniques, the Quadruple Series Capacitor (QSC) [1] and the SiN springs [2]. The quality factor measured in the WLCSP is larger than 100 at 1GHz. The capacitance can be changed from 1.4pF to 5pF by a step of 0.45pF.