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Dive into the research topics where Taro Sugizaki is active.

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Featured researches published by Taro Sugizaki.


symposium on vlsi technology | 2003

Novel multi-bit SONOS type flash memory using a high-k charge trapping layer

Taro Sugizaki; M. Kobayashi; M. Ishidao; Hiroshi Minakata; Masaomi Yamaguchi; Yasuyuki Tamura; Yoshihiro Sugiyama; Toshiro Nakanishi; H. Tanaka

We demonstrated SONOS flash memory with a SiO/sub 2//High-k/SiO/sub 2/ structure based on a 2-bit/cell scheme. We evaluated three kinds of high-k dielectric films which were Si/sub 3/N/sub 4/, Al/sub 2/O/sub 3/ and HfO/sub 2/. Among these films, Al/sub 2/O/sub 3/ showed superior retention characteristics. The charge loss amount of Al/sub 2/O/sub 3/ at 150/spl deg/C is almost the same as that of Si/sub 3/N/sub 4/ at 25/spl deg/C. HfO/sub 2/ showed poor retention characteristics. In addition, we have found that each film has a different charge loss mechanism. We speculate that Si/sub 3/N/sub 4/ causes vertical charge migration, Al/sub 2/O/sub 3/ causes scarcely any leakage, and HfO/sub 2/ causes lateral charge migration. As a consequence, Al/sub 2/O/sub 3/ is very suitable for a charge trapping layer in multi-bit SONOS memory.


Japanese Journal of Applied Physics | 2001

Dual-Thickness Gate Oxidation Technology with Halogen/Xenon Implantation for Embedded Dynamic Random Access Memories

Taro Sugizaki; Atsushi Murakoshi; Yoshio Ozawa; Toshiro Nakanishi; Kyoichi Suguro

We investigated the enhanced oxidation effect of using silicon (Si) implanted with fluorine (F), iodine (I), and xenon (Xe) before gate oxidation. I and Xe, which result in shallower implants because of their higher mass numbers, were expected to be less damaging to the Si substrate. The resultant increase in oxide thickness was found to be 20%, 80%, and 50% under F, I, and Xe implantations with a dose of 5×1014 cm-2, respectively. We found that F atoms outdiffuse to their ambient through SiO2, and that I implantation causes the greatest increase in oxide thickness. In addition, F implantation shows highly reliable dielectric characteristics, low contact resistance, and a low junction leakage current. Consequently, the F implantation process is capable of providing reliable dual-thickness gate oxide for embedded dynamic random access memories (DRAMs).


Japanese Journal of Applied Physics | 2006

Ultrahigh-Density HfO2 Nanodots for Flash Memory Scaling

Hironori Wakai; Taro Sugizaki; Takaaki Kumise; M. Kobayashi; Masaomi Yamaguchi; Toshiro Nakanishi; Hitoshi Tanaka

We have developed a simple technique for forming ultrahigh-density HfO2 nanodots with diameters of less than 3 nm and densities of 6 ×1012 cm-2. The advantage of our method is that density and diameter are controllable. The memory cell in which ultrahigh-density nanodots are used as charge trap nodes shows 2 bits/cell operation without lateral migration of trapped charges. We propose that the ultrahigh-density HfO2 nanodots are suitable as charge storage nodes in future 45 and 32 nm generations.


The Japan Society of Applied Physics | 2005

Ultra High Density HfO2-Nanodot Memory for Flash Memory Scaling

Hironori Wakai; Taro Sugizaki; Takaaki Kumise; Masahiro Kobayashi; Masaomi Yamaguchi; Toshiro Nakanishi; Hitoshi Tanaka

We have developed a simple technique for forming ultra high density HfO2 dots with diameter < 3 nm and density > 5x10 cm. Advantages of our method are that the density and diameter are controllable and the dots are well separated with average space 3 nm between dots. We propose that the ultra high density dots are suitable for charge storage node in the future 45 and 32 nm generation Flash memory.


Japanese Journal of Applied Physics | 2003

Highly Reliable Dynamic Random Access Memory Technology for Application Specific Memory with Dual Nitrogen Concentration Gate Oxynitrides Using Selective Nitrogen Implantation

Taro Sugizaki; Atsushi Murakoshi; Ryota Katsumata; Manabu Kojima; Tetsu Tanaka; Toshiro Nakanishi; Yasuo Nara

A polymetal dual gate dynamic random access memory (DRAM) for application specific memory (ASM) with dual nitrogen concentrated oxynitrides was developed for the first time. This technology uses selective nitrogen implantation performed just after gate oxidation. The nitrogen concentration of p-type metal oxide semiconductor (PMOS) in gate dielectric combined with nitrogen implantation and NO (nitric oxide) annealing is sufficiently high to suppress boron penetration, whereas that of the cell array transistor (cell-Tr) and n-type metal oxide semiconductor (NMOS) is sufficiently low to maintain the threshold voltage (Vth) without increasing the channel dosage by using only NO annealing.


Archive | 2002

Non-volatile semiconductor memory device and method for fabricating the same

M. Fukuda; Taro Sugizaki; Toshiro Nakanishi; Yasuo Nara


Archive | 2002

Manufacture system for semiconductor device with thin gate insulating film

Kiyoshi Irino; Kenichi Hikazutani; Tatsuya Kawamura; Taro Sugizaki; Satoshi Ohkubo; Toshiro Nakanishi; Kanetake Takasaki


Archive | 1999

Manufacture method and system for semiconductor device with thin gate insulating film of oxynitride

Kiyoshi Irino; Kenichi Hikazutani; Tatsuya Kawamura; Taro Sugizaki; Satoshi Ohkubo; Toshiro Nakanishi; Kanetake Takasaki


Archive | 2004

SEMICONDUCTOR STORAGE DEVICE AND MANUFACTURING METHOD THEREOF

Taro Sugizaki


Archive | 2007

Semiconductor memory device and method of manufacturing the same

Taro Sugizaki

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