Yuji Judai

A 256 kb nonvolatile ferroelectric memory at 3 V and 100 ns

One of the most important features for ferroelectric material is fast write at low voltage. This feature is used in a 256 kb nonvolatile memory that operates at 3 V power supply with a read/write time of 100 ns. Active current is 3 mA at 200 ns cycle time at 3 V for battery operation. The cell consists of 1 transistor and 1 capacitor per bit (1T1C) permitting a high level of integration. For low-voltage low-power operation, use is made of a preset reference-cell circuit, wordline boost circuits with a ferroelectric boosting capacitor and a divided-cell plate circuit.<<ETX>>

Ferroelectric Nonvolatile Memory Technology and Its Applications

Nonvolatile memory utilizing ferroelectric material is expected to be the ultimate memory due to its theoretical low power operation and fast access. We integrated a ferroelectric thin film using a standard complementary metal-oxide-semiconductor (CMOS) process and evaluated its basic characteristics and reliability including endurance and imprint effect. The film was prepared using a spin-on sol-gel method. A ferroelectric thin film formed using liquid source misted chemical deposition (LSMCD) was found to have almost the same characteristics as those of the film formed by the sol-gel method. No effects of the ferroelectric process on the CMOS transistors were observed. Design of ferroelectric memory cells and applications of the ferroelectric nonvolatile memory have been reviewed.

Integration technology of ferroelectrics and the performance of the integrated ferroelectrics

Abstract We have successfully incorporated the ferroelectric and the high dielectric constant capacitors into integrated circuits. The GaAs MMICs with BST capacitors have been widely used for cellular phones. The BST technology is also applied to a silicon CCD delayline processor for VCRs and camcorders. With respect to the ferroelectric technology with Y1, an experimentally fabricated 256k bit FeRAM has exhibited the remarkable performance of the 100 ns and 3V operation with a 1T/1C cell configuration dedicated for the FeRAM. These integrated ferroelectrics have been achieved by controlling the ferroelectric properties in thin films and incorporating the films into GaAs and silicon devices with outstanding process technology. Furthermore, we refer to the memory cell design technology which enables the FeRAM to work below 1V. Various advantages of low-voltage and high-speed operation inherent in integrated ferroelectrics will be emphasized on the intelligent microelectronics applications toward the next m...

Voltage Shift Effect on Retention Failure in Ferroelectric Memories

We investigated the origin of retention failure in ferroelectric memories (FeRAMs) with SrBi2(Ta, Nb)2O9 (SBTN) memory cell capacitors by considering the time-dependent behavior of polarization vs. voltage (P-V ) curves of the capacitors during high-temperature storage. Since the SBTN capacitors exhibited no marked decrease in the nonvolatile component of polarization even after high-temperature storage, we focused on the effect of voltage shift observed in P-V curves. We calculated bitline voltage along the storage from the P-V curves and the bitline capacitance, and successfully estimated a decrease in the bitline voltage, which is in agreement with the retention failure in FeRAMs. In addition, the calculation indicated that the lifetime limited by the retention failure in FeRAMs with SBTN capacitors at 125°C exceeds 10 years.

Highly-reliable ferroelectric memory technology with bismuth-layer structured thin films (Y-1 family)

A highly-reliable ferroelectric memory (FeRAM) which ensures retention of data written at a low voltage of 2.5 V and humidity resistance for 10 years under a high temperature of 70/spl deg/C has been successfully developed for the first time. These excellent characteristics have been attained by a newly developed ferroelectric material with mixed superlattice crystal of Y-1 family and a integration technology which makes the use of pl-SiN passivation possible.

Embedded ferroelectric memory technology with completely encapsulated hydrogen barrier structure

A 0.18-/spl mu/m system LSI embedded ferroelectric memory (FeRAM) operating at a very low voltage has been developed for the first time. The low-voltage operation has been attained by newly developed stacked ferroelectric capacitors completely encapsulated by hydrogen barriers, which enable us to eliminate hydrogen reduction of the ferroelectric thin film during the back end of the line process including FSG, tungsten CVD (W-CVD), and plasma CVD SiN (p-SiN) passivation. A fabricated 1-Mbit one-transistor one-capacitor SrBi/sub 2/(Ta/sub x/Nb/sub 1-x/)/sub 2/O/sub 9/ (SBTN)-based embedded FeRAM operates at a low voltage of 1.1 V and ensures the endurance cycles up to 10/sup 12/ at 85/spl deg/C and the data retention time up to 1000 h at 125/spl deg/C, which is the most promising for mass production of 0.18-/spl mu/m low-power system LSI-embedded FeRAM and beyond.

Advanced LSI embedded with FeRAM for contactless IC cards and its manufacturing technology

Abstract High performance LSIs embedded with ferroelectric random access memory (FeRAM) for contactless IC cards are now commercially available. The emphasis is placed on the materials solution with SrBi2(Ta,Nb)2O9 (SBTN) which enables to exploit the potential performance of FeRAMs for composite logic/microcontroller LSIs operating at high speeds and low powers. The leading-edge 0.6-μm and double-level-metal FeRAM technology produces microcontroller-embedded LSIs with 14-kbit or 64-kbit FeRAM. A mature 0.8-μm and single-level-metal process has been built to maximize the die yield. Yields exceeding 90% indicate the excellent process stability. Product qualification data have proven the robust FeRAM technologies.

Non-volatile memories using SrBi2Ta2O9 ferroelectrics

Abstract Ferroelectric non-volatile memories (FENVM) are fabricated using spin-coat and fire deposition of the SrBi2Ta2O9 layered perovskite ferroelectric. Test memories using a 2 transistor-2 capacitor bit cell, top contacts to capacitors and single level metal were fabricated. We report here on the integration and electrical characteristics of fully functional 1 Kbit test memories.

A highly reliable ferroelectric memory technology with SrBi/sub 2/Ta/sub 2/O/sub 9/-based material and metal covering cell structure

A multilevel metal process-based highly reliable ferroelectric memory (FeRAM) has been developed. Highly reliable characteristics have been attained by two techniques. One is a newly developed ferroelectric material with mixed superlattice crystal of SrBi/sub 2/(Ta/sub x/,Nb/sub 1-x/)/sub 2/O/sub 9/ and Bi/sub 2/ (Ta/sub x/,Nb/sub 1-x/)O/sub 6/. Which provides an elevated remnant polarization while keeping a low coercive voltage. The other is a metal covering memory cell structure which makes the use of plasma silicon nitride (p-SiN) passivation possible without reduction of the ferroelectric thin film by a hydrogen plasma during p-SiN deposition, which results in no B degradation of the characteristics of cell capacitors. The FeRAM cell capacitors with the above newly developed ferroelectric material and metal covering structure have been fabricated by using a 0.6-/spl mu/ double level metal process. The fabricated cell capacitors show highly reliable characteristics such as the ensured retention of data written at a low voltage of 2.4 V and humidity resistance for 10 y under a high temperature of 70/spl deg/C, which is promising for commercialization of FeRAM and its embedded LSIs.