Krishna Parat

A Program Disturb Model and Channel Leakage Current Study for Sub-20 nm nand Flash Cells

We have developed a program-disturb model to characterize the channel potential of the program-inhibited string during NAND flash cell programming. This model includes cell-to-cell capacitances from 3-D technology computer-aided design simulation and leakage currents associated with the boosted channel. We studied the program-disturb characteristics of sub-30-nm NAND cells using a delayed programming pulse method. The simulation results agree with the experimental data very well and show quantitative impacts of junction leakage current, band-to-band tunneling (BTBT) current, Fowler-Nordheim tunneling current, and channel capacitance on the program disturb. We further discuss the cell-scaling trend and identify that the BTBT current can be a dominant mechanism for the program disturb of sub-20-nm NAND cells.

Scaling directions for 2D and 3D NAND cells

This paper describes NAND cell scaling directions for 20nm and beyond. Many of the 2D NAND cell scaling challenges can be resolved by a planar floating gate (FG) cell. Scaling directions and key technology requirements for 3D NAND are also discussed.

Investigation of ballistic current in scaled Floating-gate NAND FLASH and a solution

Cell-to-cell interference constraints dictate that the Floating-gate (FG) of NAND FLASH cells be scaled down to very small thicknesses of a few nm. For the first time, we investigate and quantify the ballistic transport that occurs across ultra-thin poly-Si FGs during programming and experimentally determine its mean free path. This ballistic current has an adverse impact on the reliability of the Inter-poly dielectric (IPD) and potentially limits scaling. We have also demonstrated a solution to this problem in the form of an ultra-thin metal FG and have shown three orders of magnitude lesser ballistic current than poly-Si of same thickness. Further, we have demonstrated functional metal FG down to 3 nm.

A floating gate based 3D NAND technology with CMOS under array

NAND Flash has followed Moores law of scaling for several generations. With the minimum half-pitch going below 20nm, transition to a 3D NAND cell is required to continue the scaling. This paper describes a floating gate based 3D NAND technology with superior cell characteristics relative to 2D NAND, and CMOS under array for high Gb/mm2 density.

25nm 64Gb MLC NAND technology and scaling challenges invited paper

A highly manufacturable 25nm 64Gb NAND technology has been developed. Many physical and electrical scaling challenges were overcome. Severe scaling challenges have to be overcome to continue NAND scaling.

A 90 nm 512 Mb 166 MHz multilevel cell flash memory with 1.5 MByte/s programming

A 2b/cell flash memory in 90 nm triple-well CMOS technology achieves 1.5 MB/s programming and 166 MHz synchronous operation. The design features 2-row programming, optimized program control hardware, 3 transistor x-decoder with negative deselected rows and configurable output buffers. The die is 42.5 mm/sup 2/ with a cell size of 0.076 /spl mu/m/sup 2/.

Protection of high voltage power and programming pins

Electrostatic discharge (ESD) protection of an inte- grated circuits (ICs) high voltage power pins is achieved without damage to thin oxides by dividing the steady-state voltage and arranging weak forward bias of the diodes of a cantilever clamp. Also, programming pins are protected by cantilever clamps of various kinds, including some which turn on when breakdown is detected and turn off after is powered up.

Statistical Modeling of Leakage Currents Through SiO 2 /High-κ Dielectrics Stacks for Non-Volatile Memory Applications

We present here a statistical Monte Carlo (MC) simulator modeling leakage currents across SiO2/high-kappa dielectric stacks. We show that simulations accurately reproduce experimental currents measured at various temperatures on capacitors with different high-k dielectric stacks. We exploit statistical simulations to investigate the impact of high-kappapsilas traps on leakage current distribution for flash memory applications. We demonstrate that the high defectiveness typical of high-k materials strongly reduces the potential improvement due to the introduction of band-gap engineered high-kappa tunnel dielectric stacks. In this regard, the simulator is a useful tool to optimize high-kappa tunnel stacks and to improve technology reliability issues related to flash memory applications.

Operational Voltage Reduction of Flash Memory Using High-

We explore the performance of symmetric (low-k/high-k/low-k) and asymmetric (low-k/high-k) composite tunnel barriers with conventional Flash constraints of retention, erase, read and program disturbs. Simulations, including five different high-k materials, were performed under these criteria to minimize the programming voltage Vprog. Among all constraints, we find read disturb to be the most restrictive both in terms of lowering Vprog and choosing the high-k materials for such stacks. Furthermore, the symmetric barrier stack is found to be more promising versus the asymmetric barrier stack. For the common read disturb voltages of 2.5 and 3.6 V, the lowest Vprog of ~ 4 and 5 V, respectively (relative to the floating gate), are obtained. In addition, the maximum required operating Flash voltage is found to be 30% -40% lower than the prevalent voltages.

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Lateral bipolar n/sup +/pn/sup +/ devices, with thick field oxide (TFO) separating the collector and emitter, are often used in snapback mode as protection devices for MOS ESD circuit protection. ESD testing for Human Body Model (HBM), Machine Model (MM) and Charged Device Model (CDM) waveforms was performed on a family of TFO cells which varied the gate length (bipolar base width) as the experimental parameter. For MM and CDM, the data showed a dependence of withstand voltage on the gate length, indicating that longer gate lengths improve performance; while for HBM, withstand voltage was independent of the gate length. The devices exhibited failure modes that manifested as low level current leakage. Failure analysis identified the current leakage sites as melt filaments primarily localized at the TFO ends. Filament distribution was seen to be a function of gate length for MM. Two possible mechanisms are presented to account for the observed filament distribution and follow up experiments are suggested to test the validity of each.