Terence Kane

Electromigration-resistance enhancement with CoWP or CuMn for advanced Cu interconnects

Suppressing Cu diffusion along the Cu/Cap interface has proven to be one of the most effective ways to enhance the electromigration (EM) resistance of advanced Cu interconnects. Two methods, depositing a thin layer of CoWP on the Cu surface and doping the Cu seed layer with Mn, are presented in this paper. While each effectively enhanced the EM performance, they behaved somewhat differently in improving the line-depletion and via-depletion EM performance. CoWP functioned primarily as a Cu surface modifier and did not alter the Cu diffusion behavior below the surface, making Cu interconnects capped with CoWP very sensitive to defects in the via. As a result, the hardware processed with CoWP had greatly increased EM failure times, but also had large variability in failure times and activation energy. On the other hand, the hardware with the CuMn seed layer relied on Mn segregation to the Cu surface to slow down the Cu diffusion, plus Mn also may have diffused to grain boundaries and defective areas of the liner. Although the EM failure times of Cu interconnects with CuMn seed in some cases were not as long as those with CoWP, the variability and sensitivity to process defects was reduced.

Investigation of emerging middle-of-line poly gate-to-diffusion contact reliability issues

The minimum insulator spacing between the polysilicon control gate (PC) and the diffusion contacts (CA) in advanced VLSI circuits is aggressively shrinking due to continuous technology scaling. Meanwhile, rapid adoptions of new materials such as metal gate, epitaxial SiGe source /drain, stress liner, and copper contact together with new device configurations such as raised source/drain and FinFET may further exacerbate the PC-CA dielectric reliability. SRAM yield loss and functional stress failures of both SRAM and DRAM chips due to middle-of-line (MOL) PC-CA shorts and early breakdown have been observed during the course of technology development at 32nm. Therefore, the leakage and breakdown of middle-of-line (MOL) PC-to-CA dielectric is rapidly becoming an emerging reliability issue for a successful technology development. In this paper, a comprehensive investigation of MOL PC-to-CA reliability issues at 32nm technology node was conducted. A new qualification methodology was developed to assure PC-to-CA reliability at an acceptable level.

Geometry, kinetics, and short length effects of electromigration in Mn doped Cu interconnects at the 32nm technology node

Mn doping in Cu seed has been used to improve EM performance at the 32nm technology node. This paper will show that on an optimized process with CuMn there were different degrees of EM enhancement for geometric variations including line width and electron flow direction. In addition, kinetics experiments on several geometries resulted in activation energies in the range of 0.95-1.33eV. Finally, the Blech threshold (jL)c=338mA/um was derived from the experimental data on various line lengths and current densities.

Through-Cobalt Self Forming Barrier (tCoSFB) for Cu/ULK BEOL: A novel concept for advanced technology nodes

Through-Co self-forming-barrier (tCoSFB) metallization scheme is introduced, with Cu gap-fill capability down to 7 nm-node dimensions. Mn atoms from doped-seedlayer diffuse through CVD-Co wetting layer, to form TaMnxOy barrier, with integrity proven by vertical-trench triangular-voltage-sweep and barrier-oxidation tests. tCoSFB scheme enables 32% and 45% lower line and via resistance, respectively at 10 nm node dimensions, while achieving superior EM performance to competitive TaN/Co and TaN/Ru-based barriers.

Comprehensive investigations of CoWP metal-cap impacts on low-k TDDB for 32nm technology application

as the current-carrying capability of a copper line is reduced due to interconnect dimension shrinkage, self-aligned CoWP metal-cap has been reported to be helpful to improve degraded electromigration (EM) reliability. However, adoption of the metal cap in general further exacerbates the already problematic low-k dielectric TDDB reliability at 32nm and beyond. This paper provides a comprehensive study of CoWP metal-cap impacts on low-k TDDB for 32nm technology application. It was found that CoWP could induce a severe degradation of low-k TDDB if its process is not optimized, and its impacts on dense low-k and porous ultra low-k (ULK) dielectrics were different. An optimized CoWP process with the least defect density could lead to an acceptable TDDB performance as compared to the control for both dense low-k and porous ULK dielectrics, while showing substantial improvements in EM and stress migration (SM).

Electromigration and resistivity in on-chip Cu, Co and Ru damascene nanowires

Electromigration and resistivity of Cu, Co and Ru on-chip interconnection have been investigated. A similar resistivity size effect increase was observed in Cu, Co, and Ru. The effect of liners and cap, e.g. Ta, Co, Ru and SiCxNyHz, on Cu/interface resistivity was not found to be significant. Multilevel Cu, Co or Ru back-end-of-line interconnects were fabricated using 10 nm node technology wafer processing steps. EM in 22 nm to 88 nm wide Co lines, 24 nm wide Cu with and without a thin Co cap and 24 nm wide Ru lines were tested. These data showed that Cu with a Co cap, Co and Ru had highly reliable EM, although Ru was better than Co and Co was better Cu. The electromigration activation energies for Cu with Co cap and Co were found to be 1.5–1.6 eV and 2.1–2.7 eV, respectively.

Comparison of key fine-line BEOL metallization schemes for beyond 7 nm node

For beyond 7 nm node BEOL, line resistance (R) is assessed among four metallization schemes: Ru; Co; Cu with TaN/Ru barrier, and Cu with through-cobalt self-forming barrier (tCoSFB) [1]. Line-R vs. linewidth of Cu fine wires with TaN/Ru barrier crosses over with barrier-less Ru and Co wires for beyond-7 nm node dimensions, whereas Cu with tCoSFB remains competitive, with the lowest line R for 7 nm and beyond. Our study suggests promise of this last scheme to meet requirements in line R and EM reliability.

14nm BEOL TDDB reliability testing and defect analysis

14nm BEOL (back end of line) TDDB (time to dielectric defect breakdown) test site structures successfully detect reliability defects but pose significant challenges in defect analysis At these advanced technology nodes, the reduction in copper land cross sectional area is accompanied by increased current density and electromigration failure rates. TDDB reliability test structures must be sensitive to capturing reliability defects. These same TDDB test site structures combined with porous ultra low-k (ULK) dielectric films represent real challenges in localizing and then determining BEOL reliability defects. Defect localization is difficult due to the complexity of these multiple metal layers along with the presence of the porous, low k dielectric films which exhibit shrinkage or void formation when exposed to an e-beam/FIB ion beam > 1 keV. Due to the porosity of these ULK dielectric films, they are especially susceptible to gallium ion implantation. It has been reported elsewhere that suppressing copper diffusion at the copper land/cap interface can be achieved by depositing a thin layer of CoWP and doping the copper seed layer with manganese [15, 16, 17]. However, a method for analytically confirming that these approaches for suppressing the copper diffusion do not affect TDDB performance/electromigration behavior must be demonstrated.

Nano CV probe characterization analysis comparison with conventional CV probe pad analysis

The introduction of nano CV characterization of discrete MOSFET devices and the method of performing scanning capacitance imaging has been previously presented.1 By nano probing at CA contact level discrete MOSFET devices that are routinely analyzed at probe pad level with conventional CV measurements, a means of comparison can be established to compare the results obtained by both methods. More importantly, the nano CV measurements obtained at CA contact level can be validated by this comparison2-6 This paper will describe nano CV measurements of discrete devices and show comparison results obtained at probe pad level that confirms the validity and accuracy of nano CV measurements.

300mm wafer Atomic force probe characterization methodology

The laboratory practice of employing atomic force probing (AFP) using AFP current imaging and Nanoprobe Capacitance-Voltage Spectroscopy (NCVS) at contact level (CA) for identfication of front end of line (FEOL) defects in MOSFET devices, especially for silicon on insulator applications has been extensively detailed [1,2,3].