Robert L. Franch

A 2-ns cycle, 3.8-ns access 512-kb CMOS ECL SRAM with a fully pipelined architecture

The authors describe a 512 K CMOS static RAM (SRAM) with emitter-coupled-logic (ECL) interfaces which has a 2-ns cycle time and a 3.8-ns access time, both of which are valid for random READ/WRITE operations. The CMOS technology and the physical organization of the chip are briefly discussed, and the pipelined architecture of the chip is described. Detailed measurements of internal chip waveforms demonstrating 2-ns cycle time operation are presented. The impact of wire RC delays on performance is discussed. Circuit examples that demonstrate the implementation of the pipelined architecture are included. Measurements of operating margins, access time, and cycle time are outlined. >

A room temperature 0.1 /spl mu/m CMOS on SOI

An advanced 0.1 /spl mu/m CMOS technology on SOI is presented. In order to minimize short channel effects, relatively thick nondepleted (0.15 /spl mu/m) SOI film, highly nonuniform channel doping and source-drain extension-halo were used. Excellent short channel effects (SCE) down to channel lengths below 0.1 /spl mu/m were obtained. It is shown that undepleted SOI results in better short channel effect when compared to ultrathin depleted SOI. Devices with little short channel effect all the way to below 500 /spl Aring/ effective channel length were obtained. Furthermore, utilization of source-drain extension-halo minimizes the bipolar effect inherent in the floating body. These devices were applied to a variety of circuits: Very high speeds were obtained: Unloaded delay was 20 ps, unloaded NAND (FI=FO=3) was 64 ps, and loaded NAND (FI=FO=3, C/sub L/=0.3 pF) delay was 130 ps at supply of 1.8 V. This technology was applied to a self-resetting 512 K SRAM. Access times of 2.5 ns at 1.5 V and 3.5 ns at 1.0 V were obtained. >

A 4.6GHz resonant global clock distribution network

A resonant global clock-distribution network operating at 4.6GHz is designed in a 90nm 1.0V CMOS technology. Unique to this approach is the set of on-chip spiral inductors that resonate with the clock capacitance, resulting in 20% recycling of global clock power.

Fast CMOS ECL receivers with 100-mV worst-case sensitivity

CMOS emitter-coupled logic (ECL) receiver circuits consisting of a differential-amplifier stage and a CMOS inverter are shown to convert 100-mV input signals to on-chip CMOS levels even with worst-case parameter variations in a 5-V 1- mu m technology. Two different receiver circuits are used to cover a range of power supply options; a third circuit provides a comparison case. The differential amplifiers feature built-in feedback compensation for common-mode parameter variations. The differential input devices are designed with large widths, minimum channel lengths, and an interleaved layout to enhance gain, speed, and margin for differential mismatches. The simplicity of the circuits and the effectiveness of the built-in compensation facilitate analysis. Partitioning and simplifying assumptions are used to thoroughly test the worst case without complex simulations, while providing insight into the design process. >

6.6+ GHz Low Vmin, read and half select disturb-free 1.2 Mb SRAM

A fully functional read and half select disturb-free 1.2 Mb SRAM is demonstrated. Measured results show an operating range of 0.4 V to 1.5 V and -25degC to 100degC, speed of 6.6+ GHz at IV, 25degC and yield of 90-100%.

A 15-ns CMOS 64K RAM

The RAM was built using a technology with self-aligned TiSi/SUB 2/, single-level metal, an average minimum feature size of 1.35 /spl mu/m, and a minimum effective channel length of 1.1 /spl mu/m. An access of 10 ns is possible with the word line stitched on a second level of metal and some minor redesign. High speed is achieved through innovative circuits and design concepts. Novel CMOS circuits include a sense-amp set signal generator, a row decoder, and an input circuit. A layout-rule-independent graphics tool, which was used for the artwork design, is discussed.

SOI for a 1-volt CMOS technology and application to a 512 Kb SRAM with 3.5 ns access time

In this paper a CMOS technology that is optimum for low voltage (in the I-volt range) applications is presented. Thin but undepleted SOI is used as the substrate, which gives low junction capacitance and no body effect. Furthermore floating body effects causes a reduction of subthreshold slope at high drain bias. This lowers the high-V/sub DS/ threshold to be used, which increases the current drive without significant increase in the off-current. This technology was applied to a high performance 512 Kb SRAM. Access time of 3.5 ns at 1 V was obtained.<<ETX>>

A novel borderless contact/interconnect technology using aluminum oxide etch stop for high performance SRAM and logic

To keep pace with scaled technology and the requirements of SRAM for embedded high speed microprocessor cache, we use borderless contacts with an Al/sub 2/O/sub 3/ etch-stop and a combination of damascene and metal RIE local interconnect to achieve bulk 6T CMOS SRAM cell sizes from 34 to 15 /spl mu/m/sup 2/ (2-->4 Mb). The Al/sub 2/O/sub 3/ etch stop is RIE etched allowing the simultaneous formation of dense borderless contacts and low-resistance local interconnect, unlike previous approaches that wet etch the Al/sub 2/O/sub 3/. We have fabricated 64 K CMOS SRAMs with 5 ns access time suitable for 2 Mb embedded 2.5 V, 0.25 pm L/sub EFF/ SRAM technology using salicide, oxide planarization, dry etched Al/sub 2/O/sub 3/ etch stop, W damascene local interconnect layer, and two level AlCu metal. We have extended this technology to 4 Mb SRAM cells using a polycide gate stack damascene MO with contact to diffusion that is borderless to both gate and isolation edges, a second metal RIE local interconnect, and using a scaled device design.<<ETX>>

A 20-ns 128-kbit*4 high speed DRAM with 330-Mbit/s data rate

The authors describe a high-speed DRAM (HSDRAM), designed primarily for high performance, while retaining the density advantage of the one-transistor DRAM cell. The 128-kb*4, 78-mm/sup 2/ chip shows a random access time of 20 ns and a column access time of 7.5 ns, measured at 5.0 V, 25 degrees C, and 50-pF load. A 256-b*4 high-speed page mode is provided which has 12-ns cycle into 60 pF, resulting in a data rate of 330 Mb/s. Additional measurements on HSDRAM further demonstrate that DRAM operation in a high-speed regime is not precluded by noise, power, wiring delay, and soft error rate. The device is implemented in a 1.0 mu m n-well CMOS process. >

A subnanosecond 5-kbit bipolar ECL RAM

The authors describe a subnanosecond 512*10-b bipolar ECL RAM using a 1.2- mu m silicon-filled trench-isolated double-poly self-aligned bipolar technology in conjunction with a novel sense-amplifier reference circuit configuration. A 5-kb RAM with an access time of 0.85 ns at a power dissipation of 2.4 W is realized in a chip area of 3.4*4.4 mm/sup 2/. >