Teruyoshi Hatanaka

Through-Silicon Via Design for a 3-D Solid-State Drive System With Boost Converter in a Package

A 3-D solid-state drive system with through-silicon via (TSV) technology and boost converter is presented in this paper. The proposed boost converter enables the supply voltage reduction to 1.8 V and smaller NAND Flash memory chips. From the simulation results, the conventional bonding-wire technology can achieve only eight NAND chip integrations not only due to their structural problem but also due to the performance degradation. On the other hand, 128 NAND Flash memory chips can be integrated into a package with full-copper TSVs and the proposed system has about 1.70 μs of rise time for 20 V, 74.2 nJ of the energy dissipation, and 225 μm2 of additional Si area consumption for a NAND chip. Even if poly-Si TSVs are used, because of the process restriction, 64 NAND chips can be stacked with about 34% longer rise time and 22% degradation of energy dissipation compared to a full-copper TSV by grinding the Si-substrate to 10 μm .

Ferroelectric (Fe)-NAND Flash Memory With Batch Write Algorithm and Smart Data Store to the Nonvolatile Page Buffer for Data Center Application High-Speed and Highly Reliable Enterprise Solid-State Drives

A ferroelectric (Fe)-NAND flash memory with a batch write algorithm and a smart data store to the nonvolatile page buffer is proposed. An enterprise solid-state drive (SSD) for a data center is a future promising market of NAND flash memories. The critical problem for such an enterprise SSD is a slow random write. The write unit in a NAND flash memory is a page, 4-8 KBytes. Because the minimum write unit of the operating system is a sector, 512 Bytes, a random write to write a smaller data than a page size frequently happens, which creates a garbage. As a garbage accumulates, a garbage collection is performed to increase a workable memory capacity. The garbage collection takes as much as 100 ms, which is 100 times longer than a page program time, 800 μs, and thus causes a serious performance degradation. In the proposed Fe-NAND flash memory, the data fragmentation in a random write is removed by introducing a batch write algorithm where a page buffer in the Fe-NAND flash memory temporarily stores a program data. The memory cell program starts after the program data as much as the page size accumulates in page buffers. As the data fragmentation is eliminated, the SSD performance can double. In addition, the nonvolatile page buffer realizes a power-outage-immune highly reliable operation. With a low program/erase voltage of 6 V and a high endurance of 100 million cycles, the proposed Fe-NAND flash memory is most suitable for a highly reliable highspeed low-power data-center-application enterprise SSD.

A 1.0V power supply, 9.5GByte/sec write speed, Single-Cell Self-Boost program scheme for Ferroelectric NAND Flash SSD

A Single-Cell Self-Boost (SCSB) program scheme is proposed to achieve a 1.0V power supply operation in Ferroelectric (Fe-) NAND flash memories. In the proposed SCSB scheme, only the channel voltage of the cell to which the program voltage VPGM is applied is self-boosted in the program-inhibit NAND string. The proposed program scheme shows an excellent tolerance to the program disturb at the power supply voltage, VCC=1.0V. The power consumption of the Fe-NAND at VCC=1.0V decreases by 86% compared with the conventional floating gate (FG-) NAND at VCC=1.8V without degrading the write speed. The number of NAND chips written simultaneously in Solid-State Drives (SSD) increases by 6.9 times. As a result, the 9.5GByte/sec write throughput of the Fe-NAND SSD is achieved for an enterprise application.

A 0.5V operation, 32% lower active power, 42% lower leakage current, ferroelectric 6T-SRAM with V TH self-adjusting function for 60% larger St atic Noise Margin

A 0.5V 6T-SRAM with ferroelectric (Fe-) FETs is proposed and experimentally demonstrated for the first time. The proposed SRAM has a unique configuration to apply the body of NMOS and PMOS with VDD and VSS. During the read and the hold, the VTH of Fe-FETs automatically changes to increase the static noise margin, SNM, by 60%. During the sand-by, the VTH of the proposed SRAM cell increases to decrease the leakage current by 42%. In case of the read, the VTH of the read transistor decreases and increases the cell read current to achieve the fast read. During the write, the VTH of the SRAM cell dynamically changes and assist the cell data to flip, realizing a write assist function. The enlarged SNM realizes the VDD reduction by 0.11V, which decreases the active power, f x C x VDD2, by 32%. Since the transistor count is minimized to 6 which is similar to the conventional SRAM, the proposed SRAM realizes the smallest area.

Highly reliable, high speed and low power NAND flash memory-based Solid State Drives (SSDs)

SSDs and emerging storage class non-volatile semiconductor memories such as PCRAM, FeRAM, RRAM and MRAM have enabled innovations in various nano-scale VLSI memory systems for personal computers, multimedia applications and enterprise servers. This paper provides a comprehensive review on various state-of-the-art memory system architectures and related memory circuits for the highly reliable, high speed and low power NAND flash memory based SSDs.

NAND Controller System With Channel Number Detection and Feedback for Power-Efficient High-Speed 3D-SSD

This paper proposes a NAND controller system with a NAND channel number detector for 3D-integrated SSD. The control techniques of a program-voltage generator and an I/O frequency are proposed to enhance the SSD performance. This paper presents the solutions for the problems such as the rising time degradation and the increased power consumption caused by multi-channel parallel operation. The proposed NAND channel number detector automatically detects the number of accessed channels, that is, the number of NAND chips written at the same time. Based on the number of accessed channels, the intelligent program-voltage booster adaptively optimizes the switching clock. As a result, the proposed 3D-SSD realizes both the fastest write and the lowest energy consumption. The proposed 3D-SSD increases the write speed by 60% and decreases the energy consumption of the booster by 32%. Moreover, a dynamic I/O frequency control scheme is proposed for the future high speed I/O 3D-SSD. By selecting the adequate I/O frequencies based on the accessed number of channels, the summation of the SSD and the I/O power consumption is kept below 3.5 W even if 24 channels are operated in parallel.

A Negative Word-Line Voltage Negatively-Incremental Erase Pulse Scheme with ΔVTH = 1/6ΔVERASE for Enterprise Solid-State Drive Application Ferroelectric-NAND Flash Memories

A negative word-line voltage negatively-incremental erase pulse scheme is proposed for the enterprise solid-state drive (SSD) application ferroelectric (Fe)-NAND flash memories. The negative word-line voltage erase accelerates the erase pulse ramp-up from 1 ms of the conventional well erase to 2 µs and a 200 µs/page erase is realized. The erase characteristics with various erase pulse shape such as the fixed erase pulse, the variable time erase pulse, and the proposed negatively-incremental erase pulse for the Fe-NAND cells are investigated. With the proposed scheme, the erase voltage, VERASE decreases by ΔVERASE. The measured VTH shift, ΔVTH, is constant at 1/6ΔVERASE, which is different from that of the floating-gate NAND cells where ΔVTH = ΔVERASE. The mechanism of the constant ΔVTH is discussed with the major and the minor polarization–electric field curves. By combining the proposed negatively-incremental erase scheme with the bit-by-bit verify, a narrow erase VTH distribution of 0.07 V is achieved with ΔVERASE of 0.4 V.

A zero V TH memory cell ferroelectric-NAND flash memory with 32% read disturb, 24% program disturb, 10% data retention improvement for enterprise SSD

A zero V<inf>TH</inf> memory cell scheme for the Ferroelectric (Fe)-NAND flash memory is proposed. In the zero V<inf>TH</inf> memory cell scheme, the middle of V<inf>TH</inf> of erased and programmed cells is 0V. Based on the measurement, this paper shows for the first time that the reliability of a Fe-NAND cell such as the data retention, read disturb, and program disturb is best optimized in the proposed zero V<inf>TH</inf> cell. The measured V<inf>TH</inf> shift due to the read disturb, program disturb and data retention decreases by 32%, 24% and 10%, respectively. Contrarily, in the negative V<inf>TH</inf> cell where the middle of V<inf>TH</inf> of erased and programmed cells is negative, the V<inf>TH</inf> shift during the data retention is as much as 0.49V and unacceptably large. In the conventional positive V<inf>TH</inf> cell where the middle of V<inf>TH</inf> of erased and programmed cells is positive suffers from a sever read and program disturb. The measured results are drastically different from those of the conventional floating-gate NAND cell where the negative V<inf>TH</inf> cell is most suitable in terms of the reliability.

A 0.5-V Six-Transistor Static Random Access Memory with Ferroelectric-Gate Field Effect Transistors

A 0.5 V six-transistor static random access memory (6T-SRAM) with ferroelectric-gate field-effect-transistors (Fe-FETs) is proposed and experimentally demonstrated for the first time. During the read and the hold, the threshold voltage (VTH) of Fe-FETs automatically changes to increase the static noise margin (SNM) by 60%. During the stand-by, the VTH of the proposed SRAM cell increases to decrease the leakage current by 42%. In case of the read, the VTH of the read transistor decreases and increases the cell read current to achieve the fast read. During the write, the VTH of the SRAM cell dynamically changes and assist the cell data to flip, realizing a write assist function. The enlarged SNM realizes the VDD reduction by 0.11 V, which decreases the active power by 32%. The proposed SRAM layout is the same as the conventional 6T-SRAM and there is no area penalty.

A 3D-Integration method to compensate output voltage degradation of boost converter for compact Solid-State-Drives

This paper demonstrates the program-voltage (20 V) booster operations with stacked Si-chips for 3D-integrated Solid-State-Drives. The magnetic field radiated by the switching current of the boost converter induces the eddy current in the conductor. The eddy current graduates the boost converter performance due to the lowered inductance of the coil. The effects on the performance of the boost converter as a function of the distance from the coil to conductor are investigated. The 3D-SSD requires the >; 0.84 mm space between the coil and the conductor to generate the program-voltage of 20 V. By inserting NAND flash memory chips between the coil and the conductor, the 3D-SSD can be successfully realized without the output voltage degradation.