Shuhei Tanakamaru

Over-10×-extended-lifetime 76%-reduced-error solid-state drives (SSDs) with error-prediction LDPC architecture and error-recovery scheme

This paper presents solid-state drives (SSDs) with two high reliability techniques. First, an error-prediction (EP) low-density-parity-check (LDPC) error-correcting code (ECC) that realizes an over 10× extended lifetime. Second, an error-recovery (ER) scheme that decreases the program-disturb error rate and the data-retention error rate by 74% and 56%, respectively.

95%-lower-BER 43%-lower-power intelligent solid-state drive (SSD) with asymmetric coding and stripe pattern elimination algorithm

This paper presents intelligent solid-state drives (SSDs), which decrease memory errors by 95% and reduce power consumption by 43%. Figure 11.4.1 shows the measured memory cell error in the data retention and program disturb of 4X, 3X and 2Xnm NAND flash memories. As the memory size decreases, both data retention and program disturb errors increase due to the interference, random telegraph noise and reduced electrons [1]. In the scaled NAND, the electric field in the channel increases [2] and the program disturb due to GIDL-induced hot electron injection becomes more significant (Fig. 11.4.1(c)). In conventional SSDs, 20 to 40b correction per 1KB codeword error-correcting code (ECC) is used to correct errors [3]. As stronger codes, such as LDPC, are developed [4], the capability of ECC is close to the Shannon limit of a few percent error correction. Thus, the additional high-reliability scheme is required. As the feature size decreases, the power consumption increases due to the increased bit-line capacitance of NAND [5]. As the space between bitlines decreases, the inter bitline capacitance increases. To overcome reliability and power problems in SSDs, this paper describes two technologies. Asymmetric coding improves memory-cell reliability by 95% without access-time penalty. Stripe pattern elimination algorithm eliminates the worst program data pattern and decreases the power during the program by 43% without circuit area or access time overhead.

Error-Prediction LDPC and Error-Recovery Schemes for Highly Reliable Solid-State Drives (SSDs)

Highly reliable solid-state drives (SSDs) with error-prediction low-density parity-check (EP-LDPC) and error-recovery schemes are proposed. Since the reliability of the nand flash memory of the SSD is seriously degraded as the scaling, the conventional error-correction scheme is becoming useless. Thus, LDPC error-correcting code (ECC) is considered to be the next-generation ECC for SSD. However, many read cycles are required and the LDPC scheme consumes an unacceptably long read time. To solve this problem, the proposed EP-LDPC scheme realizes the 7 × fewer sequential read cycles than the conventional LDPC scheme. Instead of reading repeatedly, the EP-LDPC scheme estimates errors from VTH, write/erase cycles, data-retention time, and inter-cell coupling information. The bit error rate (BER) estimation is based on the prerecorded table which stores the relations among write/erase cycles, data-retention time, neighboring cell data, and BER. As a result, the acceptable data-retention time of the SSD increases by more than 10 ×. Additionally, the proposed error-recovery scheme is executed and reduces the bit error if the BER of the data exceeds the error-correction capability of EP-LDPC scheme. Program-disturb error-recovery pulse and data-retention error-recovery pulse reduce the BER of the nand flash memory by 76% and 56%, respectively.

Highly Reliable and Low Power SSD Using Asymmetric Coding and Stripe Bitline-Pattern Elimination Programming

Highly reliable and low power solid-state drive (SSD) is proposed. Through the analysis based on measured error rate in the SSDs with NAND flash memories, the memory cell error shows the asymmetric characteristic in multilevel cell (MLC) NAND flash memories. The proposed asymmetric coding increases the number of “1” s or “0” s of the programming data to reduce the data retention error. The numbers of the memory cells in the higher VTH states are reduced. The memory cell error is reduced by 90% with the asymmetric coding. On the other hand, the inter bit-line capacitance significantly increases with the scaling of memory cells. The bit-line charging current becomes unacceptably large. To decrease the write power consumption, the stripe pattern elimination algorithm (SPEA) is proposed. The SPEA eliminates the column-stripe pattern which consumes the maximum power to charge all of the inter bit-line capacitance in a NAND chip. Theoretical analyses are given for both the asymmetric coding and the SPEA. The asymmetric coding and the SPEA can be used together with the other highly reliable or low power techniques such as intelligent interleaving and adaptive code selection scheme and realizes the high reliability and low power consumption.

Elimination of half select disturb in 8T-SRAM by local injected electron asymmetric pass gate transistor

8T-SRAM cell with asymmetric pass gate transistor by local electron injection is proposed to solve half select disturb. Two types of electron injection scheme: both side injection scheme and self-repair one side injection scheme are analyzed comprehensively for 65nm technology node 8T-SRAM cell and also for 6T-SRAM cell. This paper shows that in the 6T-SRAM with the local injected electrons [4] the read speed degrades by as much as 6.3 times. In contrast, the proposed 8T-SRAM cell with the self-repair one side injection scheme is most suitable to solve the conflict of the half select disturb, write disturb and read speed. In the proposed 8T-SRAM, the disturb margin increases by 141% without write margin or read speed degradation. The proposed scheme has no process or area penalty compared with the standard CMOS-process 8T-SRAM.

Error-prediction analyses in 1X, 2X and 3Xnm NAND flash memories for system-level reliability improvement of solid-state drives (SSDs)

The system-level reliability of solid-state drives (SSDs) is investigated with 1X, 2X and 3Xnm NAND flash memories. The reliability degradation of NAND with scaling is an serious issue. Advanced ECC with signal processing such as error-prediction low-density parity-check (EP-LDPC) and error recovery (ER) scheme will be needed in the future SSDs. In this paper, the NAND reliability information used for EP-LDPC and ER is examined. System-level reliability with conventional ECC and EP-LDPC is measured.

Unified solid-state-storage architecture with NAND flash memory and ReRAM that tolerates 32× higher BER for big-data applications

Unified solid-state storage (USSS) provides high error tolerance with four techniques: reverse-mirroring (RM), error-reduction synthesis (ERS), page-RAID, and error-masking (EM). The acceptable raw bit-error rate (ABER) of NAND flash memory is enhanced by 32×, or endurance or data-retention time effectively extends by 4.2 or 34×, respectively. ABER is defined to realize BER after ECC below 10-15.

19.6 Hybrid storage of ReRAM/TLC NAND Flash with RAID-5/6 for cloud data centers

A hybrid storage architecture of ReRAM and TLC (3b/cell) NAND Flash with RAID-5/6 is developed to meet cloud data-center requirements of reliability, speed and capacity. The storage controller enhances reliability and performance through five techniques with minimal area overhead. The first three approaches, (i) flexible RRef (FR), (ii) adaptive asymmetric coding (AAC), and (iii) verify trials reduction (VTR), are applied to 50nm ReRAM to improve the bit-error rate (BER) by 69% and performance by 97%. Techniques (iv) balanced RAID-5/6 and (v) bits/cell optimization (BCO) are applied to 2Xnm TLC NAND to reduce the failure rate by 98% and extend the lifetime (write/erase (W/E) cycles) by >22×, respectively.

Post-manufacturing, 17-times acceptable raw bit error rate enhancement, dynamic codeword transition ECC scheme for highly reliable solid-state drives, SSDs

A dynamic codeword transition ECC scheme is proposed for highly reliable solid-state drives, SSDs. By monitoring the error number or the write / erase cycles, the ECC codeword dynamically increases from 512Byte (+parity) to 1KByte, 2KByte, 4KByte…32KByte. The proposed ECC with a larger codeword decreases the failure rate after ECC. As a result, the acceptable raw bit error rate, BER, before ECC is enhanced. Assuming a NAND Flash memory which requires 8-bit correction in 512Byte codeword ECC, a 17-times higher acceptable raw BER than the conventional fixed 512Byte codeword ECC is realized for the mobile phone application without an interleaving. For the MP3 player, digital-still camera and high-speed memory card applications with a dual channel interleaving, 15-times higher acceptable raw BER is achieved. Finally, for the SSD application with 8 channel interleaving, 13-times higher acceptable raw BER is realized. Because the parity rate per codeword is the same in each ECC codeword, no additional memory area is required. Note that the reliability of SSD is improved after the manufacturing without cost penalty. Compared with the conventional ECC with the fixed large 32KByte codeword, the proposed scheme achieves a better performance and a lower power consumption by introducing the “best-effort” type operation. In the proposed scheme, during the most of the lifetime of SSD, a weak ECC with a shorter codeword such as 512Byte (+parity), 1KByte and 2KByte is used and a 2.6 times better performance and a 98% lower power consumption is realized. At the life-end of SSD, a strong ECC with a 32KByte codeword is used and the highly reliable operation is achieved.

Improvement of Read Margin and Its Distribution by

A VTH mismatch self-repair scheme in 6T-SRAM with asymmetric pass gate transistor by post-process local electron injection is proposed. Local electron injection is automatically and simultaneously achieved to either pass gate transistor that most increases the read margin for each cell without investigating its characteristics. The proposed asymmetric VTH shift is twice as large as the conventional scheme without process and cell area penalty. Measurement results show 20% increase in SNM without write degradation by the asymmetric PG transistor. The proposed scheme also enhances the minimum read margin by 70% while reducing read margin distribution by 20%, thanks to the self-repair function.