Tetsu Morooka

Impact of additional factors in threshold voltage variability of metal/high-k gate stacks and its reduction by controlling crystalline structure and grain size in the metal gates

We have clarified that, in a metal/high-k gate stack, as well as the variability introduced by random dopant fluctuations (RDF), the threshold voltage variability (TVV) is attributable to the crystal structure and grain size in the metal gate. We have successfully eliminated this additional factor by reducing the grain size in the metal gate. We demonstrated that the incorporation of C into TiN metal gates transforms the crystalline film into an amorphous one, effecting a reduction in the TVV in HfSiON pFET devices. We observed that the TVV of C-incorporated TiN devices was dominated by RDF, indicating that the additional factor due to the metal gate had been diminished.

Physical model of the PBTI and TDDB of la incorporated HfSiON gate dielectrics with pre-existing and stress-induced defects

We have clarified the impact on reliability of La incorporation into the HfSiON gate dielectrics nMOSFETs (PBTI, TDDB). Although La incorporation is effective for pre-existing defect suppression, stress induced defect generation is more sensitive to stress voltage and temperature. This is caused by the elevation of the energy level of oxygen vacancy and high ionicity of La-O bond. The origin of defects is thought to be oxygen vacancy related defects, generated under positive stress and they are common to PBTI and TDDB degradation.

Single Metal/Dual High-k Gate Stack with Low V th and Precise Gate Profile Control for Highly Manufacturable Aggressively Scaled CMISFETs

We have proposed a single metal/dual high-k (SMDH), low-Vth gate stack for aggressively scaled CMISFETs. The Vth is controlled by MgO- and Al2O3-containing high-k for n and pMISFETs, respectively. The gate profile can be more easily controlled by taking advantage of a common W/TiN gate stack on both high-ks. We have successfully obtained 0.21 and -0.33 V of Vth for a 1-mum long n and pMISFET by the proposed SMDH gate stacks. We also found that MgO suppresses PBTI and that it enhances electron mobility.

Negatively charged deep level defects generated by Yttrium and Lanthanum incorporation into HfO 2 for V th adjustment, and the impact on TDDB, PBTI and 1/f noise

We studied the impact of Yttrium and Lanthanum incorporation into HfO2 on reliability (TDDB, PBTI and 1/f noise). They introduce smaller Weibull β values and early failure in TDDB, with negative shift in PBTI. They are caused by the negatively charged interstitial oxygen defect generated by Yttrium and Lanthanum incorporation. The effect of Lanthanum is larger than that of Yttrium. It can be explained by the larger ion radius and molecular volume of La2O3 than Y2O3. On the other hand, they are effective in noise reduction, as an effect of interface state density reduction. The key point in fabricating low Vth and highly reliable MOSFETs is the technology for suppression of this interstitial oxygen defect generation.

Study of a Negative Threshold Voltage Shift in Positive Bias Temperature Instability and a Positive Threshold Voltage Shift the Negative Bias Temperature Instability of Yttrium-Doped HfO2 Gate Dielectrics

We have studied unusual Vth shifts in the positive bias temperature instability (PBTI) and negative bias temperature instability (NBTI) of yttrium-doped HfO2 gate dielectrics. Both positive and negative stress conditions introduce shifts in opposite directions for yttrium-doped HfO2 in the low stress region. That is, a negative shift under a positive bias and a positive shift under a negative bias were observed. This is due to yttrium-related defects, with electron detrapping for PBTI and electron trapping for NBTI. Such defect formation can be suppressed by incorporating nitrogen into HfO2.

Improvement of Device Characteristics for TiN Gate p-Type Metal?Insulator?Semiconductor Field-Effect Transistor with Al2O3-Capped HfO2 Dielectrics by Controlling Al2O3 Diffusion Annealing Process

We have investigated the effect of postdeposition annealing (PDA) of Al2O3-capped HfO2 films on the flatband voltage (Vfb) shift and threshold voltage (Vt) variation in TiN gate p-type metal–insulator–semiconductor field-effect transistors (pMISFETs). We found that optimizing the PDA conditions to diffuse Al2O3 into the HfO2 films is a key factor for controlling Vfb, and high-temperature PDA immediately after Al2O3 deposition induces a positive Vfb shift. Additional Vt variation was observed when the PDA temperatures after Al2O3 deposition were 850 and 950 °C. In contrast, a higher temperature PDA at 1050 °C after Al2O3 deposition can suppress Vt variation to almost the same level as that obtained in a HfO2 film without an Al2O3-cap layer, although the equivalent oxide thickness (EOT) increases. We also found that superior device characteristics, such as low Vt, suppression of Vt variation, and suppression of EOT increase, were obtained by performing PDA before Al2O3 deposition.

Proposal of Single Metal/Dual High-

We have proposed a single metal/dual high-k gate stack for aggressively scaled complementary metal-insulator-semiconductor field-effect transistors (MISFETs). The threshold voltage is controlled by the dual high-k dielectrics, such as MgO- and Al2O3-containing HfSiON for n- and p-type MISFETs, respectively. The gate profile is precisely controlled by taking advantage of a common gate electrode, which will suppress the variation in device performance. Based on this device concept, we have actually fabricated W/TiN/HfMgSiON n-type MISFETs and W/TiN/HfAlSiO p-type MISFETs and have successfully demonstrated a low threshold voltage operation for both of n- and p-type MISFETs.

k

Introduction Application of Laor Y-doped HfO2 film for the gate dielectric film is expected for smaller EOT, thus higher dielectric permittivity (higher-k), with lower threshold voltage of high performance metal/high-k gate-stacked CMOSFETs [1]. A mixing process of Laor Y-oxide capped HfO2 with high-temperature annealing for the diffusion of the dopant has been proposed as a promising candidate for the fabrication process, namely “capping process”. Crystallinity of the Laor Y-doped HfO2 obtained by the capping process must be understood for developing the fabrication process of the CMOSFETs. Kita et al. reported that the La doping leads to amorphous phase of HfO2 and that the Y doping leads to crystalline phase of HfO2 demonstrated with a doping process of a combination of a film deposition with co-sputtering of Laand Hf-oxide and post-deposition annealing [2, 3]. In the capping process, it is considered that the film crystallinity of the doped HfO2 is determined by the diffusion of the dopant with the annealing for diffusion and the crystallinity of base-HfO2 before capping. In this study, we investigate transformation of crystalline structure of HfO2 formed on SiO2 by Laor Ydoping paying much attention to the crystallinity of the base-HfO2 film.