Tetsunori Wada

Two-dimensional simulation and measurement of high-performance MOSFETs made on a very thin SOI film

Thinning effects on the device characteristics of silicon-on-insulator (SOI) MOSFETs are discussed. Two-dimensional/two-carrier device simulation revealed the following advantages. An n-channel MOSFET with 500-AA-SOI thickness exhibited a high-punchthrough resistance as well as an improved subthreshold swing down to a deep submicrometer region, even if the film was nearly intrinsic. A capacitance coupling model has been proposed to explain these subthreshold characteristics. The kink elimination effect, which was attributed to a significantly reduced hole density in the SOI film, was reproduced. The low-field channel mobility exhibited a significant increase, which was ascribed to a decrease in the vertical electric field. Moreover, the current-overshoot phenomenon associated with the switching operation was suppressed. Excess holes recombine with electrons quickly after the gate turn-on, bringing about a stabilized potential in the SOI substrate. Experiments were also carried out to verify the simulation. >

Effects of microscopic fluctuations in dopant distributions on MOSFET threshold voltage

The effects of fluctuations in dopant distribution on the MOSFET threshold voltage and their dependence on the scaling were investigated using device simulation. The simulation indicates that the microscopic fluctuations in dopant distribution not only induce threshold-voltage value. It was found that the threshold-voltage value deviation is mostly affected by fluctuating dopant distribution at the substrate surface, rather than throughout the depletion layer. Discussion incorporating microscopic fluctuations in surface electric potential, due to fluctuating dopant distribution, explained not only deviations but also the mean value lowering of the threshold voltage in the simulation. >

Scaling the MOS transistor below 0.1 /spl mu/m: methodology, device structures, and technology requirements

This work is a systematic investigation of the feasibility of MOSFETs with a gate length below 0.1 /spl mu/m. Limits imposed on the scalability of oxide thickness and supply voltage require a new scaling methodology which allows these parameters to be maintained constant. The feasibility of achieving sub-0.1 /spl mu/m MOSFETs in this way is evaluated through simulations of the electrical characteristics of several different device structures and by addressing the most important issues related to the scaling down to ultra-short gate lengths. This study forms a valuable starting point for the understanding of technological requirements for future ULSI. >

Analysis of the drain breakdown mechanism in ultra-thin-film SOI MOSFETs

The drain breakdown phenomenon in ultra-thin-film (silicon-on-insulator) SOI MOSFETs has been studied. Two-dimensional simulation revealed that the thinning of the SOI film brings about an increase in the drain electric field due to the two-dimensional effect, causing a significant lowering in the drain breakdown voltage, as has been commonly seen in ultra-thin-film SOI MOSFETs. The simulation also showed that the lowered drain breakdown voltage recovered almost to its original value when the drain SOI thickness was restored, suggesting that the drain structure, rather than the source, plays a major role in determining the drain breakdown voltage. Experiments using an asymmetric device structure supported this hypothesis, showing that the breakdown voltage was mostly dependent on the drain structure, the initial potential barrier height at the source-SOI-body junction being only a minor factor. Transient simulation was also carried out to investigate the detailed breakdown process, showing that holes accumulate near the source-SOI-body junction at a high drain bias, eventually forward-biasing the junction. These results indicate that a careful drain design and/or proper choice of the SOI thickness as well as the supply voltage are quite important for realizing high performance of ultra-thin-film SOI MOSFETs. >

Analysis of kink characteristics in Silicon-on-insulator MOSFET's using two-carrier modeling

An exact SOI device simulator applicable to prediction of the transistor characteristics in high-current region is developed. In the simulator, the basic two-dimensional Poissons and current continuity equations are numerically solved under steady-state condition. To obtain a stable and rapid convergence in the numerical scheme, a newly developed alternative step solving method is implemented. Using this simulator, the drain current kink effect, a typical phenomenon for substrate-floating devices, is exactly simulated for the first time. The physical mechanism of this phenomenon is also clarified. The simulated results indicate that kink effects are suppressed by using Iow-lifetime SOI substrates.

Three-dimensional analysis of subthreshold swing and transconductance for fully-recessed-oxide (trench) isolated 1/4- mu m-width MOSFETs

The dependence of MOSFET gate controllability on the field-isolation scheme is investigated using three-dimensional simulation. It is found that a fully-recessed-oxide (trench) isolated MOSFET has a steep subthreshold characteristic and high transconductance in comparison with a nonrecessed device. These features result from the small depletion capacitance due to the crowding of the gates fringing field at the channel edge. It is also found that the gate and diffused line capacitances in the case of fully-recessed-oxide isolation are small, so that high switching speed operation can be expected. These features are enhanced with a reduction in the channel width, especially for lower-submicrometer-width MOSFETs. A drawback of a fully-recessed-oxide MOSFETs is its low threshold voltage. However, the leakage current is not as large as that inferred from the inverse narrow-channel effect because of its steep subthreshold characteristic. Several countermeasures for this low threshold voltage are discussed. >

A study of nonequilibrium diffusion modeling-applications to rapid thermal annealing and advanced bipolar technologies

A nonequilibrium diffusion model has been developed to study the influence of point defects on dopant redistribution, especially for transient enhanced diffusion. The coupled equations for point defects, substitutional impurities, and impurities/point defect pairs are solved under nonequilibriums condition. Charged species are included and the Poisson equation is solved. The characteristics and domain of validity of this model have been investigated. Indications are suggested to predict the conditions under which a steady-state model can be used. In the case of high-concentration predisposition, enhanced diffusion is observed and concave or exponential profiles are obtained for very short-time diffusion. Applications are presented for oxide diffusion sources. The generality of the model is confirmed by long-time diffusion behavior and by the influence of phosphorus diffusion on the boron buried layer. Anomalous effects observed during RTA steps after ion implantation are also well reproduced by the model. Successful comparisons with experiments are reported for boron and for actual bipolar structures, with coupled arsenic/boron diffusion in a 0.5- mu m BiCMOS process. >

High performance SOIMOSFET using ultra-thin SOI film

Advantages of using an ultra-thin SOI substrate for SOIMOSFET are discussed using a 2- carrier/2-dimensional simulation. Ultra-thin SOIMOSFET has been shown to possess sharp subthreshold slope and high punchthrough resistance nearly independent of doping concentration. Low field mobility in ultra-thin SOIMOSFET has been predicted to increase up to approximately the maximum value which is obtainable in the inversion layer. The disappearance of kink associated with thinning the SOI film has been reproduced in the simulation. Moreover, it has been found that the current overshoot is virtually suppressed in thin-SOI MOSFET, enabling one to obtain a stable current irrespective of pulse intervals. These results bring SOIMOSFETs an anticipation as a promising alternative for bulk MOSFETs in the application of high speed and small-featured devices.

Steep subthreshold characteristic and enhanced transconductance of fully-recessed oxide (trench) isolated 1/4 µm width MOSFETs

This paper describes the dependence of MOSFET gate-controllability on the field isolation scheme. It is found that a fully-recessed oxide (trench) isolated MOSFET has a sharp cutoff characteristic and high transconductance in comparison with a non-recessed one. These features of the fully-recessed oxide MOSFET are due to the crowding of the gates fringing field at the channel edge. It is also found that the gate and diffused line capacitances for the fully-recessed oxide isolation are small so that high switching speed operation can be expected.

A supervised simulation system for process and device designs based on a geometrical data interface

A supervised simulation system for two-dimensional simulation has been developed covering the range from pattern layout to process simulation and also to device simulation. The system features a system controller for module programs, and the feasibility of module programs based on an intermediate topography data format with which data go between the module programs. The system controller can automatically generate appropriate jobs, assigning pertinent input data. The topography data acts as an interface through process simulation and up to device simulation. The system will eliminate laborious work for designers and greatly reduce the time required for process and device designs.