Tetsuo Yamasaki

An elastic pipeline mechanism by self-timed circuits

An elastic pipeline mechanism that is especially suitable for data-driven processors is described. With the elastic pipeline scheme, a large processing rate and a smooth data stream in the pipeline are realized at the same time. Two types of self-timed circuits, which are used for data-transfer control circuits in the elastic pipeline, are proposed. Using different types of transfer control circuits, two loop-shaped elastic pipeline mechanisms have been implemented on test chips and are compared with each other. One of these chips demonstrated that the data throughput in the pipeline was 55 megawords per second and that the critical path within a pipeline stage corresponded to 16 inverter delays. This indicates the possibility of high-performance data-driven processors. >

VLSI implementation of a variable-length pipeline scheme for data-driven processors

A VLSI-oriented variable-length pipeline structure for data-driven processors is presented. Ordinary inline pipelines have the problem of minimizing the average total processing time through the pipeline, since subdivision of a function along the pipeline is usually optimized for the most complex operations in spite of the fact that simpler operations need fewer stages. As a solution to this problem, a variable-length pipeline scheme in which data go through only the necessary stages according to information contained within is proposed. The scheme has been implemented on a test chip to verify performance. The chip demonstrated a minimum fall-through time (data transmission time from input to output) of 14.4 ns and a data transmission rate in the pipeline of 59 megaword/s (that is, 1/16.9 ns) as a first-in first-out (FIFO) store. By modifying the data transfer control and allocating the processing functions corresponding to the data interval of 16.9 ns, this scheme is applicable as a high-performance processing unit for data-driven processors. >