Tetsuo Yamasaki
Mitsubishi
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Featured researches published by Tetsuo Yamasaki.
IEEE Journal of Solid-state Circuits | 1988
Shinji Komori; Hidehiro Takata; Toshiyuki Tamura; Fumiyasu Asai; Takio Ohno; O. Tomisawa; Tetsuo Yamasaki; Kenji Shima; K. Asada; Hiroaki Terada
An elastic pipeline mechanism that is especially suitable for data-driven processors is described. With the elastic pipeline scheme, a large processing rate and a smooth data stream in the pipeline are realized at the same time. Two types of self-timed circuits, which are used for data-transfer control circuits in the elastic pipeline, are proposed. Using different types of transfer control circuits, two loop-shaped elastic pipeline mechanisms have been implemented on test chips and are compared with each other. One of these chips demonstrated that the data throughput in the pipeline was 55 megawords per second and that the critical path within a pipeline stage corresponded to 16 inverter delays. This indicates the possibility of high-performance data-driven processors. >
IEEE Journal of Solid-state Circuits | 1989
Tetsuo Yamasaki; Kenji Shima; Shinji Komori; Hidehiro Takata; Toshiyuki Tamura; Fumiyasu Asai; Takio Ohno; O. Tomisawa; Hiroaki Terada
A VLSI-oriented variable-length pipeline structure for data-driven processors is presented. Ordinary inline pipelines have the problem of minimizing the average total processing time through the pipeline, since subdivision of a function along the pipeline is usually optimized for the most complex operations in spite of the fact that simpler operations need fewer stages. As a solution to this problem, a variable-length pipeline scheme in which data go through only the necessary stages according to information contained within is proposed. The scheme has been implemented on a test chip to verify performance. The chip demonstrated a minimum fall-through time (data transmission time from input to output) of 14.4 ns and a data transmission rate in the pipeline of 59 megaword/s (that is, 1/16.9 ns) as a first-in first-out (FIFO) store. By modifying the data transfer control and allocating the processing functions corresponding to the data interval of 16.9 ns, this scheme is applicable as a high-performance processing unit for data-driven processors. >
Archive | 1993
Tetsuo Yamasaki; Kenji Shima; Shinji Komori; Koichi Munakata; Yoshie Inaoka
Archive | 1989
Hidehiro Takata; Shinji Komori; Toshiyuki Tamura; Tetsuo Yamasaki; Kenji Shima
Archive | 1990
Souichi Miyata; Satoshi Matsumoto; Shinichi Yoshida; Toshiya Okamoto; Takeshi Fukuhara; Shinji Komori; Tetsuo Yamasaki; Kenji Shima
Archive | 1988
Tetsuo Yamasaki; Kenji Shima; Mitsuo Meichi; Shinji Komori; Hidehiro Takata
Archive | 1996
Hiroaki Terada; Hiroaki Nishikawa; Shinichi Yoshida; Shunji Hine; Youichiro Nishikawa; Shuji Hara; Kenji Shima; Yoshie Inaoka; Tetsuo Yamasaki
Archive | 1988
Shinji Komori; Hidehiro Takata; Toshiyuki Tamura; Fumiyasu Asai; Tetsuo Yamasaki; Kenji Shima
IEEE Journal of Solid-state Circuits | 1989
Shinji Komori; Hidehiro Takata; Toshiyuki Tamura; Fumiyasu Asai; Takio Ohno; Osamu Tomisawa; Tetsuo Yamasaki; Kenji Shima; Hiroaki Nishikawa; Hiroaki Terada
Archive | 1994
Makoto Tanaka; Kinya Ogino; Tetsuo Yamasaki