Fumiyasu Asai

An elastic pipeline mechanism by self-timed circuits

An elastic pipeline mechanism that is especially suitable for data-driven processors is described. With the elastic pipeline scheme, a large processing rate and a smooth data stream in the pipeline are realized at the same time. Two types of self-timed circuits, which are used for data-transfer control circuits in the elastic pipeline, are proposed. Using different types of transfer control circuits, two loop-shaped elastic pipeline mechanisms have been implemented on test chips and are compared with each other. One of these chips demonstrated that the data throughput in the pipeline was 55 megawords per second and that the critical path within a pipeline stage corresponded to 16 inverter delays. This indicates the possibility of high-performance data-driven processors. >

A 100-mega-access per second matching memory for a data-driven microprocessor

A high-throughput matching memory (MM) for a data-driven microprocessor is discussed. An MM can be constructed using a hashing memory. However, one of the biggest problems with hashing memory is the necessity for selective processing whenever hashed address conflicts occur. To eliminate this problem, the MM incorporated a small amount of associative memory (32 words*50 b) as well as the hashing memory (512 words*42 b). The matching operation is subdivided into three pipeline stages, all controlled by the elastic pipeline scheme. With this structure, an MM with a high throughput of 100-mega-access/s MM can be realized. >

A 1.8 V 36 mW DSP for the half-rate speech codec

A low-power 16-bit DSP has been developed to realize a low bit-rate speech codec. A dual datapath architecture and low-power circuit design techniques are employed to reduce power consumption. The PDC half-rate speech codec is implemented in the DSP with 36 mW at 1.8 V.

A 40 MFLOPS 32-bit floating-point processor

A 40 MFLOPS (million floating-point operations per second), 32-bit floating-point processor (FP) for a single-board data-driven processor is developed using a pipeline configuration called the elastic pipeline structure. Because there is no need to add controls for pipeline flushing by virtue of the data-driven processing principle, it is possible to employ extensively subdivided pipeline stages. The elastic mode of data transfer between pipeline stages and distributed execution controls along the pipeline result in minimum deterioration of the inherent logic switching speed. The structure of the FP is shown together with details of the ALU (arithmetic logic unit) block. The fabrication process and chip specifications are summarized.<<ETX>>

VLSI implementation of a variable-length pipeline scheme for data-driven processors

A VLSI-oriented variable-length pipeline structure for data-driven processors is presented. Ordinary inline pipelines have the problem of minimizing the average total processing time through the pipeline, since subdivision of a function along the pipeline is usually optimized for the most complex operations in spite of the fact that simpler operations need fewer stages. As a solution to this problem, a variable-length pipeline scheme in which data go through only the necessary stages according to information contained within is proposed. The scheme has been implemented on a test chip to verify performance. The chip demonstrated a minimum fall-through time (data transmission time from input to output) of 14.4 ns and a data transmission rate in the pipeline of 59 megaword/s (that is, 1/16.9 ns) as a first-in first-out (FIFO) store. By modifying the data transfer control and allocating the processing functions corresponding to the data interval of 16.9 ns, this scheme is applicable as a high-performance processing unit for data-driven processors. >

A data-driven architecture for distributed parallel processing

A single-chip data-driven microprocessor with special functions for distributed parallel processing is described. The implemented functions necessary for parallel processing are: relative addressing mode for program memory; efficient test and set operation of arbitrary data in data memory; transparent access of distributed shared memory; and dynamic load distribution among multiprocessors. With this microprocessor, practical parallel processing systems which exploit a wide area of scientific applications can be constructed.<<ETX>>