D. Fitsios

Optical Buffering for Chip Multiprocessors: A 16GHz Optical Cache Memory Architecture

We demonstrate a 16GHz physical layer optical cache memory architecture for direct mapping associativity, organized in four cache lines with every line being capable of storing two bytes of optical data. WDM formatting of both the memory address and the optical data words is exploited, while the proposed design relies on the interconnection of subsystems that comprise experimentally proven optical building blocks. The performance of the optical cache is evaluated via physical layer simulations showing successful functionality both during Read and Write operation. Going a step further and considering a higher capacity optical cache module, we present its impact when performing with true processor workload benchmarks in Chip Multiprocessor configurations, employed as a L1 cache shared among multiple cores. Its performance is compared with the conventional electronic CMP topology, where dedicated L1 electronic caches and a shared L2 cache are used, showing that the use of optical 16GHz cache can lead to performance speed-up up to 40% while reducing the cache total capacity requirements by 84%. With optical interconnects having already resulted to high-bandwidth CPU-memory bus solutions, our optical cache architecture forms a fully compatible system solution for bridging the gap between optically connected CPU-cache schemes and high-speed optical RAM cell solutions.

Ultra-compact III-V-on-Si photonic crystal memory for flip-flop operation at 5 Gb/s

We report on a photonic crystal (PhC) nanolaser based on the heterogeneous integration of a III-V PhC nanocavity on SOI, configured to operate as a Set-Reset Flip-Flop (SR-FF). The active layer is a nanobeam cavity made of a 650 nm × 285 nm InP-based wire waveguide evanescently coupled to 500 nm × 220 nm SOI wire waveguides, demonstrating a record-low footprint of only 6.2 μm2. Injection locking enables optical bistability allowing for memory operation with only 6.4 fJ/bit switching energies and <50 ps response times. Bit-level SR-FF memory operation was evaluated at 5 Gb/s with PRBS-resembling data patterns, revealing error free operation with a negative power penalty.

All-optical 3-bit counter using two cascaded stages of SOA-MZI-based T-flip-flops

We present a 3-bit all-optical counter comprising two cascaded stages of a novel optical T-Flip-Flop that employs one SOA-MZI and a feedback loop. Experimental verification is demonstrated at 8MHz using a fiber-based feedback loop implementation.

Tb/s switching fabrics for optical interconnects using heterointegration of plasmonics and silicon photonics: The FP7 PLATON approach

We present recent work that is carried out within the FP7 project PLATON on novel Tb/s switch fabric architectures and technologies for optical interconnect applications, employing heterointegration of plasmonics, silicon photonics and electronics.

On-Chip Dual-Stream DWDM Eight-Channel-Capable SOI-Based MUX s /DEMUX s With 40-GH z Channel Bandwidth

We demonstrate two 8 × 1 silicon ring resonator (RR)-based multiplexers (MUXs) integrated on the same chip for dual-stream 16-channel multiplexing/ demultiplexing applications. Cascaded second-order RRs equipped with microheaters were integrated on a silicon-on-insulator platform with the radii of MUX1 and MUX2 being ~12 and ~9 μm, respectively. The resonances of the two MUXs were thermooptically tuned in order to achieve 100-GHz channel spacing, revealing a tuning efficiency of 43 and 36 μW/GHz/RR for MUX1 and MUX2, respectively, and 352 mW total power consumption. Lower than 18 dB crosstalk and higher than 40-GHz 3-dB bandwidth was obtained for the tuned channels of the MUXs. The signal integrity when using these devices in multiplexing and demultiplexing operations was evaluated for a 4 × 10 Gb/s non-return-to-zero data stream (i.e., 10 Gb/s line rate) via bit-error-rate measurements, yielding error-free performance with up to 0.2 dB power penalty for all channels. Proofof-concept demonstration for supporting higher data rates was also realized by using three 100-GHz-spaced 25-Gb/s return-to-zero data signals (i.e., 25 Gb/s line rate) for multiplexing and demultiplexing via MUX2, resulting in error-free operation for all channels with lower than 0.3 dB power penalties.

Multi-wavelength access gate for WDM-formatted words in optical RAM row architectures

Optical RAM has emerged as a promising solution for overcoming the “Memory Wall” of electronics, indicating the use of light in RAM architectures as the approach towards enabling ps-regime memory access times. Taking a step further towards exploiting the unique wavelength properties of optical signals, we reveal new architectural perspectives in optical RAM structures by introducing WDM principles in the storage area. To this end, we demonstrate a novel SOAbased multi-wavelength Access Gate for utilization in a 4x4 WDM optical RAM bank architecture. The proposed multiwavelength Access Gate can simultaneously control random access to a 4-bit optical word, exploiting Cross-Gain-Modulation (XGM) to process 8 Bit and Bit channels encoded in 8 different wavelengths. It also suggests simpler optical RAM row architectures, allowing for the effective sharing of one multi-wavelength Access Gate for each row, substituting the eight AGs in the case of conventional optical RAM architectures. The scheme is shown to support 10Gbit/s operation for the incoming 4-bit data streams, with a power consumption of 15mW/Gbit/s. All 8 wavelength channels demonstrate error-free operation with a power penalty lower than 3 dB for all channels, compared to Back-to-Back measurements. The proposed optical RAM architecture reveals that exploiting the WDM capabilities of optical components can lead to RAM bank implementations with smarter column/row encoders/decoders, increased circuit simplicity, reduced number of active elements and associated power consumption. Moreover, exploitation of the wavelength entity can release significant potential towards reconfigurable optical cache mapping schemes when using the wavelength dimension for memory addressing.

Fabrication-tolerant optical filters for dense integration on a micron-scale SOI platform

We present the first characterization results of some cascaded interleavers that we have recently fabricated on 4 μm thick Silicon on Insulator (SOI) wafers. The filters are based on strip waveguides, micron-scale bends and compact MMIs, all components with low loss and high tolerance to fabrication errors, due to the high mode confinement in the silicon region. A thorough comparison of the found results with the theoretical model will be presented, taking into account fabrication limitations. The fabricated filters will be used in the optical RAM circuits of the RAMPLAS project funded by the European Commission.

Optical RAM-enabled cache memory and optical routing for chip multiprocessors: technologies and architectures

The processor-memory performance gap, commonly referred to as “Memory Wall” problem, owes to the speed mismatch between processor and electronic RAM clock frequencies, forcing current Chip Multiprocessor (CMP) configurations to consume more than 50% of the chip real-estate for caching purposes. In this article, we present our recent work spanning from Si-based integrated optical RAM cell architectures up to complete optical cache memory architectures for Chip Multiprocessor configurations. Moreover, we discuss on e/o router subsystems with up to Tb/s routing capacity for cache interconnection purposes within CMP configurations, currently pursued within the FP7 PhoxTrot project.

High gain 1.3-μm GaInNAs SOA with fast-gain dynamics and enhanced temperature stability

Semiconductor optical amplifiers (SOAs) are a well-established solution of optical access networks. They could prove an enabling technology for DataCom by offering extended range of active optical functionalities. However, in such costand energy-critical applications, high-integration densities increase the operational temperatures and require powerhungry external cooling. Taking a step further towards improving the cost and energy effectiveness of active optical components, we report on the development of a GaInNAs/GaAs (dilute nitride) SOA operating at 1.3μm that exhibits a gain value of 28 dB and combined with excellent temperature stability owing to the large conduction band offset between GaInNAs quantum well and GaAs barrier. Moreover, the characterization results reveal almost no gain variation around the 1320 nm region for a temperature range from 20° to 50° C. The gain recovery time attained values as short as 100 ps, allowing implementation of various signal processing functionalities at 10 Gb/s. The combined parameters are very attractive for application in photonic integrated circuits requiring uncooled operation and thus minimizing power consumption. Moreover, as a result of the insensitivity to heating issues, a higher number of active elements can be integrated on chip-scale circuitry, allowing for higher integration densities and more complex optical on-chip functions. Such component could prove essential for next generation DataCom networks.

Dual-facet coupling of SOA array on 4-μm Silicon-on-Insulator implementing a hybrid integrated SOA-MZI wavelength converter

Hybrid integration on Silicon-on-Insulator (SOI) has emerged as a practical solution for compact and high-performance Photonic Integrated Circuits (PICs). It aims at combining the cost-effectiveness and CMOS-compatibility benefits of the low-loss SOI waveguide platform with the versatile active optical functions that can be realized by III-V photonic materials. The utilization of SOI, as an integration board, with μm-scale dimensions allows for an excellent optical mode matching between silicon rib waveguides and active chips, allowing for minimal-loss coupling of the pre-fabricated IIIV components. While dual-facet coupling as well as III-V multi-element array bonding should be employed to enable enhanced active on-chip functions, so far only single side SOA bonding has been reported. In the present communication, we present a novel integration scheme that flip-chip bonds a 6-SOA array on 4-μm thick SOI technology by coupling both lateral SOA facets to the waveguides, and report on the experimental results of wavelength conversion operation of a dual-element Semiconductor Optical Amplifier – Mach Zehnder Interferometer (SOA-MZI) circuit. Thermocompression bonding was applied to integrate the pre-fabricated SOAs on SOI, with vertical and horizontal alignment performed successfully at both SOA facets. The demonstrated device has a footprint of 8.2mm x 0.3mm and experimental evaluation revealed a 12Gb/s wavelength conversion operation capability with only 0.8dB power penalty for the first SOA-MZI-on-SOI circuit and a 10Gb/s wavelength conversion operation capability with 2 dB power penalty for the second SOA-MZI circuit. Our experiments show how dual facet integration can significantly increase the level of optical functionalities achievable by flip-chip hybrid technology and pave the way for more advanced and more densely PICs.