Thomas B. Cho

A 10 b, 20 Msample/s, 35 mW pipeline A/D converter

This paper describes a 10 b, 20 Msample/s pipeline A/D converter implemented in 1.2 /spl mu/m CMOS technology which achieves a power dissipation of 35 mW at full speed operation. Circuit techniques used to achieve this level of power dissipation include digital correction to allow the use of dynamic comparators, and optimum scaling of capacitor values through the pipeline. Also, to be compatible with low voltage mixed-signal system environments, a switched capacitor (SC) circuit in each pipeline stage is implemented and operated at 3.3 V with a new high-speed, low-voltage operational amplifier and charge pump circuits. Measured performance includes 0.6 LSB of INL, 59.1 dB of SNDR (Signal-to-Noise-plus-Distortion-Ratio) for 100 kHz input at 20 Msample/s. At Nyquist sampling (10 MHz input) SNDR is 55.0 dB. Differential input range is /spl plusmn/1 V, and measured input referred RMS noise is 220 /spl mu/V. The power dissipation at 1 MS/s is below 3 mW with 58 dB of SNDR. >

A 1.9-GHz wide-band IF double conversion CMOS receiver for cordless telephone applications

A monolithic 1.9-GHz, 198-mW, 0.6-/spl mu/m CMOS receiver which meets the specifications of the Digital Enhanced Cordless Telecommunications (DECT) standard is described. All of the RF, IF, and baseband receiver components, with the exception of the frequency synthesizers, have been integrated into a single chip solution. A description is given of a wide-band IF with double conversion architecture which eliminates the need for the discrete-component noise and IF filters in addition to facilitating the eventual integration of the frequency synthesizer blocks with on-chip VCOs. The prototype device utilizes a 3.3-V supply and includes a low noise amplifier, an image-rejection mixer, and two quadrature baseband signal paths each of which includes a second-order Sallen and Key anti-alias filter, an eighth-order switched-capacitor filter network followed by a 10-b pipelined analog-to-digital converter (ADC). The experimental device has a measured receiver reference sensitivity of -90 dBm, an input referred IP3 of -7 dBm, a P/sub -1 dB/ of -24 dBm, and an image-rejection ratio of -55 dBc across the DECT bands.

A 1.9 GHz wide-band IF double conversion CMOS integrated receiver for cordless telephone applications

A number of recent efforts have concentrated on highly-integrated radio receivers using a low-cost silicon process such as CMOS. This prototype monolithic CMOS receiver combines RF and baseband functionality by taking the carrier signal at the LNA input and producing a 10 b digital baseband waveform. A wide-band intermediate frequency double conversion (WBIFDC) architecture eliminates the need for external narrow-band IF filters.

A 10-bit, 20-MS/s, 35-mW pipeline A/D converter

This paper describes a 10-bit 20-MS/s pipeline A/D converter implemented in 1.2-/spl mu/m CMOS technology which achieves a power dissipation of 35 mW at full speed operation. Circuit techniques used to achieve this level of power dissipation include operation on a 3.3 V power supply, optimum scaling of capacitor values through the pipeline, and digital correction to allow the use of dynamic comparators. Measured performance includes 0.6 LSB of INL, 59.1 dB of SNDR for 100 kHz input at 20 MS/s. At Nyquist sampling (10 MHz input), SNDR is 55.0 dB.<<ETX>>

A power-optimized CMOS baseband channel filter and ADC for cordless applications

A 3.3 V continuous-time anti-aliasing filter, 8th-order switched-capacitor channel filter and 10-bit ADC implemented in 0.6 micron CMOS for baseband channel filtering in direct conversion cordless phone receivers realizes an overall gain of 50 dB with 42 dB of gain control range. Dynamic range of the combined filter section is 87 dB, and the maximum SNDR of ADC is 54 dB at 40 MS/s. Total power dissipation of 48 mW for filters and ADC is achieved at 3.3 volts through optimum capacitor scaling in filter and pipeline ADC implementation.

Design considerations for low-power, high-speed CMOS analog/digital converters

This paper reviews architectural and circuit design considerations for realization of low power dissipation in high-speed CMOS A/D converters. Basic limitations on achievable power dissipation in MOS samplers and quantizers is first discussed. Then a number of practical design aspects are illustrated with discussion of a 10-bit, 20-Msample/s pipeline A/D converter implemented in 1.2-/spl mu/m CMOS technology which achieves a power dissipation of 35 mW at full speed operation on a 3.3 V power supply.

A 2 MHz GFSK IQ receiver for Bluetooth with DC-tolerant bit slicer

An IQ processor in 0.18 /spl mu/m CMOS implements Bluetooth low-IF functions at 2 MHz with 7/sup th/-order complex Bessel bandpass IF filter, limiter, quadricorrelator baseband FM demodulator, and differential slope sensing bit slicer. The sensitivity is -46 dBm at 0.1% BER. The chip consumes 50 mW at 1.8 V and occupies 2 mm/spl times/2.8 mm.

A VDSL2 CPE AFE in 0.15µm CMOS with integrated line driver

VDSL2 transceivers use a wide analog bandwidth to achieve bit-rates in excess of 200Mb/s. For standard 6-band VDSL2, 30MHz bandwidth is required, comprising three up-stream and three down-stream signals. Since discrete multi tone (DMT) modulation is used, distortion components for the signal chain have to be below −65dBc to fully exploit 15b-per-tone bit loading [1].

A 2.4 GHz Bluetooth transceiver in 0.18 /spl mu/m CMOS

A 2.4 GHz GFSK transceiver in 0.18 /spl mu/m CMOS implements all Bluetooth modem functions with -80 dBm input sensitivity at 0.1% BER. A baseband IQ processor implements IF functions at 2 MHz with a 7th-order complex Bessel bandpass filter, limiter, quadricorrelator baseband FM demodulator, and differential slope sensing bit slicer. The chip consumes 80 mW for RX and 50 mW for TX at 1.8 V and occupies 4.2 mm/spl times/3.5 mm.