Thomas Kauerauf

Origin of the threshold voltage instability in SiO 2 /HfO 2 dual layer gate dielectrics

The magnitude of the V/sub T/ instability in conventional MOSFETs and MOS capacitors with SiO/sub 2//HfO/sub 2/ dual-layer gate dielectrics is shown to depend strongly on the details of the measurement sequence used. By applying time-resolved measurements (capacitance-time traces and charge-pumping measurements), it is demonstrated that this behavior is caused by the fast charging and discharging of preexisting defects near the SiO/sub 2//HfO/sub 2/ interface and in the bulk of the HfO/sub 2/ layer. Based on these results, a simple defect model is proposed that can explain the complex behavior of the V/sub T/ instability in terms of structural defects as follows. 1) A defect band in the HfO/sub 2/ layer is located in energy above the Si conduction band edge. 2) The defect band shifts rapidly in energy with respect to the Fermi level in the Si substrate as the gate bias is varied. 3) The rapid energy shifts allows for efficient charging and discharging of the defects near the SiO/sub 2//HfO/sub 2/ interface by tunneling.

Ultra low-EOT (5 Å) gate-first and gate-last high performance CMOS achieved by gate-electrode optimization

A novel gate first integration approach enabling ultra low-EOT is demonstrated. HfO₂ based devices with a zero interface layer and optimized gate-electrode is used to achieve EOT and T_inv values of ˜5 Å and ˜8 Å respectively for both n and pMOS devices. The drive currents at I_off=100 nA/μm with V_DD=1 V is 1.4 mA/μm and 0.6 mA/μm (no SiGe source/drain) for n and pMOS respectively. The technology further offers low n/pMOS V_T of 0.3/-0.4V, good V_T-uniformity, and V_T-matching and very high cutoff frequencies at ˜290-340 GHz for 38 nm nMOS devices. A replacement poly gate process is used to further improve upon the pMOS effective work function. TDDB lifetimes over 10 years are reported while BTI indicates potential reliability challenges.

Characterization of the V/sub T/-instability in SiO/sub 2//HfO/sub 2/ gate dielectrics

The electrical stability of CMOS devices with conventional gate dielectrics is commonly studied using static (DC) measurement techniques. By applying the same methods to MOS devices with alternative gate dielectrics, it has been shown that alternative gate stacks suffer from severe charge trapping and that the trapped charge is not stable, leading to fast transient charging components. In this paper, time-resolved measurement techniques down to the /spl mu/s time range are applied to capture the fast transient component of the charge trapping observed in SiO/sub 2//HfO/sub 2/ dual layer gate stacks. Furthermore, its impact on the device performance and reliability of n-channel FETs is discussed.

Low Weibull slope of breakdown distributions in high-k layers

The reliability of various Al/sub 2/O/sub 3/, ZrO/sub 2/ and Al/sub 2/O/sub 3//ZrO/sub 2/ double layers with a physical oxide thickness from 3 nm to 15 nm and TiN gate electrodes was studied by measuring time-to-breakdown using gate injection and constant voltage stress. The extracted Weibull slope /spl beta/ of the breakdown distribution is found to be below 2 and shows no obvious thickness dependence. These findings deviate from previous results on intrinsic breakdown in SiO/sub 2/, where a strong thickness dependence was explained by the percolation model. Although promising performance on devices with high-k layers as dielectric can be obtained, it is argued that gate oxide reliability is likely limited by extrinsic factors.

Degradation and breakdown of 0.9 nm EOT SiO/sub 2/ ALD HfO/sub 2/metal gate stacks under positive constant voltage stress

By means of leakage current measurements, charge pumping and TDDB analysis, we construct a consistent model for the degradation and breakdown of 0.9 nm EOT atomic layer deposited (ALD) HfO2. During degradation, traps and two-trap clusters are formed in the HfO 2 giving rise to considerable SILC. The two-trap clusters subsequently wear out, finally leading to an abrupt hard breakdown. We demonstrate that 0.9 nm EOT ALD HfO2 is intrinsically reliable under constant voltage stress if hard breakdown is used as a failure criterion

Insight Into N/PBTI Mechanisms in Sub-1-nm-EOT Devices

New insights into the negative/positive bias temperature instability (N/PBTI) degradation mechanisms in the sub-1-nm equivalent oxide thickness (EOT) regime are presented in this paper. The electric field requirements suggested by the International Roadmap for Semiconductors demand an even higher value in the sub-1-nm-EOT regime, which is practically difficult to meet with the increased hole trapping mechanism involved. Thus, a fixed electric field target of 5 MV/cm is considered as well here, which might be a reasonable target to achieve. The sub-1-nm-EOT devices in this paper are obtained by adopting a thinner TiN metal gate inducing Si in-diffusion and reducing the interfacial oxide layer thickness. NBTI degradation follows an isoelectric field model in over an EOT of 1 nm due to the degradation mechanism of Si/SiO_2 interface state generation combined with a hole trapping mechanism. However, in the sub-1-nm-EOT regime, the probability of hole trapping into the gate dielectric increases, and it is strongly dependent on the thickness of the interfacial oxide layer. Several experimental proofs of this increased bulk defect effect are shown in this paper. In addition, the bulk defect affecting NBTI is shown to be mostly a preexisting defect, although the permanently generated defects are relatively higher in sub-1-nm-EOT devices. Therefore, NBTI in the sub-1-nm-EOT regime faces the lifetime limit by both electric field dependence and increased degradation by increased hole trapping into bulk defects. Further, we found a minimum interfacial layer thickness of 0.4 nm that is required to prevent the accelerated NBTI degradation by increased direct tunneling. The main degradation mechanism of PBTI in sub-1-nm EOT is the electron trapping into bulk defects, which is the same as in over 1-nm-EOT devices. This enables us to modulate the bulk defect energetic locations in the oxide and to improve PBTI.

A comprehensive reliability investigation of the voltage-, temperature- and device geometry-dependence of the gate degradation on state-of-the-art GaN-on-Si HEMTs

In this work, the gate degradation of GaN-based HEMTs is analyzed. We find that the gate degradation does not occur only beyond a critical voltage, but it has a strong voltage accelerated kinetics and a weak temperature dependence. By means of a statistical study we show that the time-to-failure can be fitted best with a Weibull distribution. By using the distribution parameters and a power law model it is possible to perform lifetime extrapolation based on the gate degradation at a defined failure level and temperature for the first time. From this elaboration, the lifetime of a given device geometry can also be extracted. Eventually, the strong bias dependence of the gate degradation reported here implies that this phenomenon should be assessed by means of a voltage-based accelerated investigation as described in this work.

Charge trapping and dielectric reliability of SiO/sub 2/-Al/sub 2/O/sub 3/ gate stacks with TiN electrodes

A detailed study on charge trapping and dielectric reliability of SiO/sub 2/-Al/sub 2/O/sub 3/ gate stacks with TiN electrodes has been carried out. Due to the inherent asymmetry of the dual layer stack all electrical properties studied were found to be strongly polarity dependent. The gate current is strongly reduced for injection from the TiN (gate) electrode compared to injection from the n-type Si substrate. For substrate injection, electron trapping occurs in the bulk of the Al/sub 2/O/sub 3/ film, whereas for gate injection mainly hole trapping near the Si substrate is observed. Furthermore, no significant interface state generation is evident for substrate injection. In case of gate injection a rapid build up of interface states occurs already at small charge fluence (q/sub inj/ /spl sim/ 1 mC/cm/sup 2/). Dielectric reliability is consistent with polarity-dependent defect generation. For gate injection the interfacial layer limits the dielectric reliability and results in low Weibull slopes independent of the Al/sub 2/O/sub 3/ thickness. In the case of substrate injection, reliability is limited by the bulk of the Al/sub 2/O/sub 3/ layer leading to a strong thickness dependence of the Weibull slope as expected by the percolation model.

Review of reliability issues in high-k/metal gate stacks

This paper reviews some of the recent learning at IMEC in reliability research on high-k gate stacks. We show how measurement, characterization techniques and physical degradation models can be transferred from SiO2 (or SiON) single layers to SiO2(SiON)/high-k stacks. In a first part, negative bias temperature instability (NBTI) is discussed. We show how interface states created at the SiO2 (or SiON)/substrate interface determine to a large extend the NBTI. Nitridation has a strong negative impact on NBTI, while thickness or composition of the high-k layer have nearly no influence. In a second part, we discuss the effect of bulk traps in the high-k layer. These traps cause fast Vt-instability and hysteresis, as well as significant positive bias temperature instability (PBTI). Additional bulk traps are created under electrical stress and form percolating paths of two or more traps causing soft breakdown (SBD). At low voltage and with metal gates, the SBD-leakage path develops into a hard breakdown (HBD) after some further wear-out time. We summarize the methodology to come to a complete reliability prediction that includes multiple SBDs and HBD. In high-k stacks, the leakage current increase due to multiple SBDs can be a reliability threat for some applications.

Stress polarity dependence of degradation and breakdown of SiO/sub 2//high-k stacks

In this paper, we summarize our findings on two material systems: SiO/sub 2//Al/sub 2/O/sub 3/ and SiO/sub 2//ZrO/sub 2/. Relatively thick high-k layers are used to avoid defect related problems and to assess the bulk properties of the layers. We show Time-Dependent Dielectric Breakdown data for both polarities and at various stress conditions. We explain how the properties of the time-to-breakdown distribution provide valuable information that can help identify the physical degradation mechanism. We demonstrate that the degradation in double layers strongly depends on the injection polarity and this can only be explained consistently if the conduction mechanism through both constitutive layers and the energy of the injected carriers are taken into account. Furthermore, we hint at how the process impact on the reliability can be observed and evaluated.