Thomas L. McDevitt

Collimated sputtering of titanium liner films to control resistance of high-aspect-ratio contacts (Abstract Only)

Consistently low contact resistance is critical to performance and reliability of CMOS devices. Shrinking cell sizes have driven contact dimensions to increasingly higher aspect ratios. Previous technologies have used conventionally sputtered Ti/TiN contact liner films to provide good metallurgical bonding and electrical conductivity between silicide—clad diffusions and tungsten contact studs. However, for high aspect-ratio contacts, step coverage of conventional PVD Ti may not be adequate. It has bcen shown that step coverage may be enhanced through the use of a collimator. A collimator is a honeycomb-like device suspended between the target and wafer. This device screens sputtered species which travel in paths with angles of incidence non-normal to the wafer surface. This paper describes the development and evaluation of a 200 mm collimated titanium process for the IBM 16 Mb-DRAM. The 16-Mb device employs TiSi2-clad diffusions which are passivated with a doped glass. Contacts are patterned and etched through the glass to open the diffusions. The contact dimensions are nominally O.6-m in diameter by 1 .2-sm deep. Following etching, a Ti/TiN bilayer is deposited onto the wafer and CVD tungsten is deposited and planarized to form the contact stud. In the 16-Mb development program Ti coverage of the bottom of the contact was found to be critical to a robust process. Titanium is known to be highly reactive and is thought to consume native oxides and RIE residuals on the suicide surface. For contact dimensions currently under consideration, step coverage of conventional PVD films was typically < 10% . Step coverage of 15-40% has been demonstrated with collimation. Comparison of contact resistance data from wafers processed with collimated and conventionally deposited liner films shows a profound improvement with coffimation. Mean contact resistance for wafers with the conventional PVD liner process is typically greater than 100 ohms, with collimation, the resistance is typically less than 5 ohms. The presentation will also summarize a large database that has been generated on process stability, collimator lifetime and particulate performance.

Damascene copper integration

The increase in ratio of wiring RC delay to the intrinsic transistor RC delay is motivating the IC industry to move from subtractive-aluminum to damascene-copper wiring. In addition to having 40% lower sheet resistance, damascene copper has significantly lower resistance and capacitance variability than subtractive-aluminum wiring due to improved reactive ion etch bias control. Damascene copper causes less plasma charging than subtractive-aluminum wiring in wire/via antenna devices and the charging can be modulated by electron shadowing during via RIE.