Stephen E. Luce

Integration of chemical-mechanical polishing into CMOS integrated circuit manufacturing

Abstract Planarization by chemical-mechanical polishing (CMP) has been exploited by IBM in the development and manufacture of CMOS products since 1985. Among the products that use this technology are the 4-Mbit DRAM (which uses polysilicon, oxide, tungsten-line and tungsten-stud planarization) and its logic family (which uses four oxide and four tungsten-stud planarization steps). CMP is also used in the planarization of oxide shallow isolation trenches, as in the 16-Mbit DRAM. Reduced sensitivity to many types of defects is possible with CMP. A wafer that is truly flat is easier to clean, eliminates step coverage concerns, provides for better photolithographic and dry etch yields, and generally minimizes complications from prior level structures. Oxide CMP reduces sensitivity to certain pre-existing defects, such as crystalline inclusions or foreign material in an interlevel dielectric. Metal CMP can reduce the incidence of intralevel shorts relative to conventional RIE processing. Random defects associated with CMP, such as slurry residues and mechanical damage, are controlled by careful optimization of the post-polish clean and of the polish process itself. Systematic defects, such as incomplete planarization over very large structures, are controlled by process optimization and prudent design limitations. These include such things as constraints on the image size, the distance between images, and/or the local pattern density. Since its introduction in the 4-Mbit DRAM, there has been a steady increase in the use of chemical-mechanical polishing in IBM CMOS products. The number of steps, processes and materials polished continue to rise, both in current and planned future products. Individual applications range from the simple removal of back-side films to complex insulator or metal planarization requiring high removal uniformity. The process tolerances delivered by CMP have decreased faster than image size, even in the face of dramatic increases in circuit and layout complexity. CMP tools are installed in IBM semiconductor manufacturing and development sites worldwide. Chemical-mechanical polish processes and applications provide unique leverage to IBM products, and are a crucial part of both current and planned IBM CMOS technologies.

Interconnect fabrication processes and the development of low-cost wiring for CMOS products

As the cost and performance of integrated circuit (IC) interconnections, or “interconnects,” become increasingly important to the development and manufacturing of successful advanced IC products, so also do underlying metallization and patterning processes. In particular, the goals of achieving product design specifications, low development cost (high and early yield), low manufacturing cost, and portability across products can only result from applying robust unit processes that combine to form integrable and scalable process modules. In this paper, we review the interconnect fabrication processes used to form currently manufactured IBM CMOS products, and describe the materials and process integration issues that motivated their selection. In addition, we identify factors which may inhibit application of the fabrication processes to future products having smaller dimensions. The review suggests that large improvements in cost and scalability can be achieved by forming dual-damascene monolithic studs/wires. Previously, the dual-damascene approach was not generally applicable because of the lack of suitable metal deposition techniques for filling high-aspect-ratio features with highly conductive metal. However, recent advances may provide that capability both for near-term applications using Al-based wiring, and also for future applications using more extendible Cu-based wiring.

Electromigration evaluation of aluminum alloys in multilevel metallization

Abstract This paper focuses on Ti/Al−2.0%Si−0.5%Cu and Ti sandwiched Al−0.5%Cu metallurgies. The electrical reliability of the two Al alloys was determined by a standard electromigration technique (elevated d.c. current and temperature) utilizing single-level and two-level interconnect structures. Transmission electron microscopy and scanning electron microscopy have been used to characterize the film microstructure formed during processing and the types of failure modes observed electrically. For a linewidth approximating film thickness, the formation of a bamboo microstructure dominated the t50 data. TACT films provided superior performance for a stripe linewidth of 2.7 μm and a maximum chain-link length of 100 μm. The common failure modes of the different metallurgies were described, with the TACT exhibiting extrusion.