Thomas Rueckes

A 4 Megabit Carbon Nanotube-based nonvolatile memory (NRAM)

A 4Mbit nonvolatile memory with a Carbon Nanotube (CNT) storage element has been manufactured in a 0.25 µm CMOS process at a production fab. The CNT storage element is integrated in BEOL, requires minimal additional processing steps, and only a single additional mask. The memory can be RESET in 50 nanoseconds and SET in 500 nanoseconds. Demonstrated read access time of the development vehicle is 50 nanoseconds. Write endurance is in excess of 10,000 cycles, and robust data retention has been demonstrated. The CNT storage element is scalable to <5 nm, and voltage and current consumption during write operations are low. As intrinsic NRAM SET & RESET times are < 1 nanosecond, improvements in performance are anticipated.

A 3D stackable Carbon Nanotube-based nonvolatile memory (NRAM)

A 4Mbit nonvolatile memory with a Carbon Nanotube (CNT) storage element has been manufactured in a 0.25 µm CMOS process at a production fab. The CNT storage element is integrated in BEOL, requires minimal additional processing steps, and only a single additional mask. The memory can be RESET in 50 nanoseconds and SET in 500 nanoseconds. Demonstrated read access time of the development vehicle is 50 nanoseconds. Write endurance is in excess of 10,000 cycles, and robust data retention has been demonstrated. The CNT storage element is scalable to <5 nm, and voltage and current consumption during write operations are low. As intrinsic NRAM SET & RESET times are < 1 nanosecond, improvements in performance are anticipated.

Investigation and Improvement of Verify-Program in Carbon Nanotube-Based Nonvolatile Memory

Carbon nanotube (CNT)-based random access memory (NRAM) cells are measured to investigate cell program at different set current compliances and temperatures. Then, a physical model is proposed to explain the mechanism of cell resistance switching. Specifically, the changes in the NRAM cell tunneling current and resistance can be attributed to the variation of the distance between CNTs. An attraction force (Fattraction), generated by electrical induction, reduces the distance, whereas a repulsion force (Frepulsion), generated by phonon-induced temperature, increases the distance. It is proposed that the dominance of these two forces is reversed during set and reset programs, possibly due to the reduction of Frepulsion in set program. Finally, two verify-reset schemes are proposed to improve the NRAM cell verify-program performance. The first proposal, multiple-pulse reset demonstrates 23% program time reduction by skipping a cell resistance read between two successive reset pulses. The second proposal, gate-pulse reset is calculated to decrease more than 40% program energy by reducing bitline charge energy in array program.

Storage element scaling impact on CNT memory retention and ON/OFF window

CNT (Carbon Nanotube) based memory (NRAM) demonstrates a beneficial scaling effect related to the patterned area of the CNT region, such that the scaled feature shows an improvement in ON/OFF resistance ratio (to ~10,000x and improved data retention relative to the original feature dimensions.

Carbon nanotube memory cell array program error analysis and tradeoff between reset voltage and verify pulses

In emerging non-volatile memories, nano-random access memory (NRAM) has advantages of small program current and high endurance compared with resistive RAM (ReRAM) and phase-change RAM (PRAM). This work comprehensively investigates NRAM set and reset program characteristics by measuring a 116 nm 4 Mbit NRAM cell array. Specifically, reset is found more dependent on reset voltage than reset current. Next, NRAM set and reset bit error rates (BERs) have less significant reduction compared with the increased ratio of set and reset pulse widths. The reset BER can also be reduced by applying multiple reset pulses. Moreover, 108 write cycles are measured on 256 bytes NRAM cells, no wear-out or broken cell is found. Finally, the program characteristics of two verify-reset schemes are compared. The maximum verify-reset voltage can be reduced by increasing the number of reset pulses.

NRAM status and prospects

Advanced memory technology based on carbon nanotubes (NRAM) has been shown to possess desired properties for implementation in a host of integrated systems due to demonstrated advantages of its operation including high speed (Nanotubes can switch state in picoseconds), high endurance (over a trillion), and low power (with essential zero standby power). The applicable integrated systems have markets that will see compound annual growth rates (CAGR) of over 62% between 2018 and 2023, with an embedded systems CAGR of 115% in 2018 to 2023 [1]. These opportunities for NRAM technology are helping drive the realization of a shift from silicon to a carbon-based memory. NRAM is made up of an interlocking matrix of carbon nanotubes, either touching or slightly separated, leading to low or higher resistance states respectively. The small movement of atoms, as opposed to electrons for traditional memories, renders NRAM with a more robust endurance and high temperature retention/operation which, along with high speed/low power, is expected to blossom in this memory technology to be a disruptive replacement for the current status quo of DRAM (dynamic RAM), SRAM (static RAM), and NAND flash memories.

Reliability study of Carbon Nanotube memory after various cycling conditions

Carbon Nanotube (CNT) memory has a simple structure, low voltage, low current, and fast switching mechanism, and endurance up to 1012 cycles has been demonstrated [1]. In order to optimize set and reset algorithms and understand the mechanisms of CNT reliability, this work studies the CNT after 107 endurance cycles for different combinations of set and reset endurance voltages. It is confirmed that set and reset cycling voltages affect the count and ratio of set and reset errors after 107. Based on measurement of a 6Mb test chip, the endurance condition in which the set voltage is lower than the reset voltage, gives the best cycling.

Reset-Check-Reverse-Flag Scheme on NRAM With 50% Bit Error Rate or 35% Parity Overhead and 16% Decoding Latency Reductions for Read-Intensive Storage Class Memory

A novel error correction scheme, called reset-checkreverse-flag (RCRF), is proposed to improve the reliability of storage class memories (SCMs). RCRF divides the conventional Bose-Chaudhuri-Hocquenghem (BCH) code length into multiple subsections. One flag bit is added to each subsection to correct program errors. By reversing the flag bit and user data, at least one reset error in each subsection can be recovered. A 4 Mbit carbon nanotube (CNT) based nano-random access memory (NRAM) cell array is measured to verify this scheme. During 108 write cycles, it is demonstrated that RCRF reduces the program bit error rate (BER) by 50% and only requires 0.4% extra array area for the flag bits. Next, BCH ECC is applied after RCRF to correct the remaining errors. Compared with the conventional BCH ECC-only approach, the proposed combination of RCRF and BCH ECC reduces parity overhead by 35% and ECC decoding latency by 16%. Therefore, RCRF is especially suited for read-intensive types of data storage, such as video and audio. On the other hand, for high endurance applications, RCRF and BCH ECC is also effective to improve the cycling reliability of resistive memories, and 50 times endurance extension is demonstrated for a 50 nm AlxOy resistive RAM (ReRAM) test chip.