Tomoko Ogura Iwasaki

Application Driven SCM and NAND Flash Hybrid SSD Design for Data-Centric Computing System

In order to efficiently store, retrieve and process big data, the data-centric computing paradigm is adopted and an application-driven storage class memory (SCM)/NAND flash hybrid solid-state drive (SSD) is designed. SSD data management algorithms minimize data movement inside the storage system and the SSD system design parameter, SCM/NAND capacity ratio, is chosen depending on the application. Design guidelines are proposed, based on the evaluation of three SCM/NAND flash hybrid SSDs with: (1) write-back (WB) cache, (2) write-optimized data management (WO-DM) and (3) read-write balanced data management (RWB-DM) algorithms. The WO-DM algorithm achieves the highest SSD performance for write-intensive applications, whereas RWB-DM is most appropriate for read-hot (frequently accessed)-random workloads. As long as the workload is not read-cold-sequential or write-cold-sequential, adding SCM to the NAND SSD system is cost-effective to boost performance. Less than 10% SCM/NAND capacity ratios provides 10x speed, compared to the NAND flash-only SSD.

Investigation and Improvement of Verify-Program in Carbon Nanotube-Based Nonvolatile Memory

Carbon nanotube (CNT)-based random access memory (NRAM) cells are measured to investigate cell program at different set current compliances and temperatures. Then, a physical model is proposed to explain the mechanism of cell resistance switching. Specifically, the changes in the NRAM cell tunneling current and resistance can be attributed to the variation of the distance between CNTs. An attraction force (Fattraction), generated by electrical induction, reduces the distance, whereas a repulsion force (Frepulsion), generated by phonon-induced temperature, increases the distance. It is proposed that the dominance of these two forces is reversed during set and reset programs, possibly due to the reduction of Frepulsion in set program. Finally, two verify-reset schemes are proposed to improve the NRAM cell verify-program performance. The first proposal, multiple-pulse reset demonstrates 23% program time reduction by skipping a cell resistance read between two successive reset pulses. The second proposal, gate-pulse reset is calculated to decrease more than 40% program energy by reducing bitline charge energy in array program.

Advanced error prediction LDPC for high-speed reliable TLC nand-based SSDs

Highly reliable solid-state drives (SSDs) with triple-level-cell (TLC) NAND flash and Advanced Error-Prediction Low-Density Parity-Check (AEP-LDPC) are proposed. To increase NAND flashs capacity, bits/cell have been doubled and tripled, which causes reliability to drastically degrade due to narrower VTH margins. Previously proposed Error-Prediction LDPC (EP-LDPC) error-correcting code (ECC) improved reliability for Multi-Level-Cell (MLC) NAND flash [4]. However, in EP-LDPC program disturb is not modeled, so precision is limited, especially in short data retention <; 2 days. Here, AEP-LDPC is proposed for TLC NAND flash. By considering effects of program disturb, data retention and floating-gate capacitive coupling, the most accurate SSDs can be realized, with high speed read capability. The SSDs data-retention time increases by more than 12x, decode iterations decrease 57% and acceptable TLC NAND BER increases by more than 2.8 ×.

Write stress reduction in 50nm Al x O y ReRAM improves endurance 1.4× and write time, energy by 17%

Novel write verification methods are proposed to improve write speed, energy and endurance of resistive random access memory (ReRAM). Flexible write stress is implemented during reset w/ verification and set w/ verification, by which the pulse width or voltage can be decremented as well as incremented. Proposed reset w/ verification and set w/ verification methods are characterized by measuring 50nm AlxOy ReRAM devices and compared against conventional methods. Improvements of 1.9× average endurance increase, or 1.4× average endurance increase with 17% write time, the reset time plus set time decrease and 17% average write energy reduction are demonstrated.

23% faster program and 40% energy reduction of carbon nanotube non-volatile memory with over 1011 endurance

Carbon nanotube (CNT) non-volatile memory provides excellent cell characteristics of >1011 endurance, low power, fast <;5ns array program, and multi-level cell (MLC) potential. For the first time, optimal program methods are investigated considering speed, power and cell variability. Discrete cells are measured and a multiple-pulse reset scheme is proposed to reduce verify-reset time and a gate pulse verify-reset scheme further reduces array program energy by 40%.

Cost, Capacity, and Performance Analyses for Hybrid SCM/NAND Flash SSD

Storage class memories (SCMs) are fast and energy-efficient solid-state memories with high endurance. However, the bit cost of SCM is higher than that of NAND flash memory due to its relative production immaturity. As a cost-effective alternative to replace the conventional NAND flash-only solid-state drive (SSD), the hybrid SCM/MLC NAND SSD is a promising next generation storage solution. It is already understood that SCM capacity requirement depends on the workload characteristics. However, the optimum SCM capacity is also determined by the latency parameters of the SCM chips themselves. Therefore, in this paper, the dependencies of SCM capacity on SCM chip latency parameters are analyzed for the hybrid SCM/MLC NAND flash SSD. From the experimental results, increasing SCM capacity to accelerate the SSD performance is feasible when the write and read latencies of the SCM are below 1 μs. Furthermore, SSD energy consumption is more dependent on write rather than read latency. Finally, optimistic and pessimistic models of SCM area cost are considered in order to optimize the cost-efficiency of the SCM chip design in the hybrid SCM/MLC NAND SSD. According to the SCM area cost models, a SCM:NAND capacity ratio of at least 1.5% with a SCM read latency of less than 630 ns is recommended for the Financial1 workload, assuming that the SCM write/read latency ratio is 5.

50 nm AlxOy resistive random access memory array program bit error reduction and high temperature operation

In order to decrease program bit error rate (BER) of array-level operation in AlxOy resistive random access memory (ReRAM), program BERs are compared by using 4 × 4 basic set and reset with verify methods on multiple 1024-bit-pages in 50 nm, mega-bit class ReRAM arrays. Further, by using an optimized reset method, 8.5% total BER reduction is obtained after 104 write cycles due to avoiding under-reset or weak reset and ameliorating over-reset caused wear-out. Then, under-set and over-set are analyzed by tuning the set word line voltage (VWL) of ±0.1 V. Moderate set current shows the best total BER. Finally, 2000 write cycles are applied at 125 and 25 °C, respectively. Reset BER increases 28.5% at 125 °C whereas set BER has little difference, by using the optimized reset method. By applying write cycles over a 25 to 125 to 25 °C temperature variation, immediate reset BER change can be found after the temperature transition.

Reliability enhancement of 1Xnm TLC for cold flash and millennium memories

Endurance and retention are measured in 1Xnm Triple Level Cell (TLC) NAND and the flexible nLC scheme (flex-nLC) is proposed to improve reliability. This method enables the use of lowest-cost TLC NAND as is, in long term storage applications such as cold flash and digital archive: millennium memory, which have 20 and 1000 years retention, respectively.

Machine Learning Prediction for 13X Endurance Enhancement in ReRAM SSD System

The variable behavior of ReRAM memory cells is modeled with machine learning. Two types of prediction are investigated, reset in the next-cycle and cell fail in the long term. A new proposal, Proactive Bit Redundancy, introduces a ML-trained Prediction Engine into the SSD controller, to predict fail cells and replace them proactively - before actual failure- by redundancy. With the Invalid Masking technique, predicted cells are marked in-place within the page, so that no extra address table is needed. Thus, with ninimal overhead, 2.85x bit error rate reduction or 13x endurance improvement is obtained based on a 50nm AlxOy testchip.

Machine learning-based proactive data retention error screening in 1Xnm TLC NAND flash

A screening method to proactively reduce data retention, as well as program disturb errors. Repeated program disturb (P.D.) measurement indicates that 25% of P.D. errors are concentrated in 3.5% of the memory cells, called PD-weak cells. PD-weak cells have 2.4× worse data retention (D.R.) than non-PD-weak cells, therefore D.R. errors are reduced by PD-weak cell screening. Proactive D.R. detection is a new capability, because conventional retention testing time is too long for chip testing. In 1Xnm TLC NAND flash, removal of PD-weak cells with <;2% overhead extends D.R. by 20%. The measurement method is described, and machine learning is applied to detect PD-weak cells. Detection rate vs. cost is also compared for 3 learning algorithms.