Sheyang Ning

19.6 Hybrid storage of ReRAM/TLC NAND Flash with RAID-5/6 for cloud data centers

A hybrid storage architecture of ReRAM and TLC (3b/cell) NAND Flash with RAID-5/6 is developed to meet cloud data-center requirements of reliability, speed and capacity. The storage controller enhances reliability and performance through five techniques with minimal area overhead. The first three approaches, (i) flexible RRef (FR), (ii) adaptive asymmetric coding (AAC), and (iii) verify trials reduction (VTR), are applied to 50nm ReRAM to improve the bit-error rate (BER) by 69% and performance by 97%. Techniques (iv) balanced RAID-5/6 and (v) bits/cell optimization (BCO) are applied to 2Xnm TLC NAND to reduce the failure rate by 98% and extend the lifetime (write/erase (W/E) cycles) by >22×, respectively.

Investigation and Improvement of Verify-Program in Carbon Nanotube-Based Nonvolatile Memory

Carbon nanotube (CNT)-based random access memory (NRAM) cells are measured to investigate cell program at different set current compliances and temperatures. Then, a physical model is proposed to explain the mechanism of cell resistance switching. Specifically, the changes in the NRAM cell tunneling current and resistance can be attributed to the variation of the distance between CNTs. An attraction force (Fattraction), generated by electrical induction, reduces the distance, whereas a repulsion force (Frepulsion), generated by phonon-induced temperature, increases the distance. It is proposed that the dominance of these two forces is reversed during set and reset programs, possibly due to the reduction of Frepulsion in set program. Finally, two verify-reset schemes are proposed to improve the NRAM cell verify-program performance. The first proposal, multiple-pulse reset demonstrates 23% program time reduction by skipping a cell resistance read between two successive reset pulses. The second proposal, gate-pulse reset is calculated to decrease more than 40% program energy by reducing bitline charge energy in array program.

Write stress reduction in 50nm Al x O y ReRAM improves endurance 1.4× and write time, energy by 17%

Novel write verification methods are proposed to improve write speed, energy and endurance of resistive random access memory (ReRAM). Flexible write stress is implemented during reset w/ verification and set w/ verification, by which the pulse width or voltage can be decremented as well as incremented. Proposed reset w/ verification and set w/ verification methods are characterized by measuring 50nm AlxOy ReRAM devices and compared against conventional methods. Improvements of 1.9× average endurance increase, or 1.4× average endurance increase with 17% write time, the reset time plus set time decrease and 17% average write energy reduction are demonstrated.

23% faster program and 40% energy reduction of carbon nanotube non-volatile memory with over 1011 endurance

Carbon nanotube (CNT) non-volatile memory provides excellent cell characteristics of >1011 endurance, low power, fast <;5ns array program, and multi-level cell (MLC) potential. For the first time, optimal program methods are investigated considering speed, power and cell variability. Discrete cells are measured and a multiple-pulse reset scheme is proposed to reduce verify-reset time and a gate pulse verify-reset scheme further reduces array program energy by 40%.

50 nm AlxOy resistive random access memory array program bit error reduction and high temperature operation

In order to decrease program bit error rate (BER) of array-level operation in AlxOy resistive random access memory (ReRAM), program BERs are compared by using 4 × 4 basic set and reset with verify methods on multiple 1024-bit-pages in 50 nm, mega-bit class ReRAM arrays. Further, by using an optimized reset method, 8.5% total BER reduction is obtained after 104 write cycles due to avoiding under-reset or weak reset and ameliorating over-reset caused wear-out. Then, under-set and over-set are analyzed by tuning the set word line voltage (VWL) of ±0.1 V. Moderate set current shows the best total BER. Finally, 2000 write cycles are applied at 125 and 25 °C, respectively. Reset BER increases 28.5% at 125 °C whereas set BER has little difference, by using the optimized reset method. By applying write cycles over a 25 to 125 to 25 °C temperature variation, immediate reset BER change can be found after the temperature transition.

Machine Learning Prediction for 13X Endurance Enhancement in ReRAM SSD System

The variable behavior of ReRAM memory cells is modeled with machine learning. Two types of prediction are investigated, reset in the next-cycle and cell fail in the long term. A new proposal, Proactive Bit Redundancy, introduces a ML-trained Prediction Engine into the SSD controller, to predict fail cells and replace them proactively - before actual failure- by redundancy. With the Invalid Masking technique, predicted cells are marked in-place within the page, so that no extra address table is needed. Thus, with ninimal overhead, 2.85x bit error rate reduction or 13x endurance improvement is obtained based on a 50nm AlxOy testchip.

0.6 V operation, 26% smaller voltage ripple, 9% energy efficient boost converter with adaptively optimized comparator bias-current for ReRAM program in low power IoT embedded applications

The Internet of Things (IoT) applies the sensors and MCUs on various machines, devices and equipment, and connect them through internet. The emerging non-volatile memory, Resistive Random Access Memory (ReRAM) is suitable for the sensor data storage because of the low voltage and low power program operation. In this paper, the proposed 0. 6 V operation, 0.27 mm2 die size boost converter is demonstrated to achieve low ReRAM program voltage ripple (Cripple) and high energy efficiency (η), simultaneously, by using the 2 μA to 8 μA adaptive comparator current (ICMP). In detail, for one ReRAM cell program, the proposed boost converter reduces VRIPPLE by 26% compared with the conventional boost converter with fixed 2 μA small ICMP. For 16 ReRAM cells program, the proposed boost converter improves 8.9% energy efficiency compared with the conventional boost converter with fixed 8 μA large ICMP.

Control gate length, spacing, channel hole diameter, and stacked layer number design for bit-cost scalable-type three-dimensional stackable NAND flash memory

A cell design for three-dimensional (3D) stackable NAND (3D NAND) flash memory are investigated with emphases on control gate length (Lg), spacing (Lspace) and channel hole diameter (Φ). The requirements for the Lg and Lspace are derived from the 3D device simulation and the effective cell size that competes with the planar NAND. The simulations reveal that Lg = Lspace = 20 nm (40 nm layer pitch) is achievable for bit-cost scalable (BiCS)-type 3D NAND with the 90 nm diameter hole. If the number of stacked layers is 22 with the layer pitch of 40 nm, the effective cell size of the 3D NAND corresponds to that of 15 nm planar NAND technology. Furthermore, cell characteristics of the macaroni body channel with various Φ are investigated. Although macaroni body channel improves cell characteristics at Φ = 90 nm, a cell with Φ = 60 nm without macaroni body structure shows better characteristics.

Carbon nanotube memory cell array program error analysis and tradeoff between reset voltage and verify pulses

In emerging non-volatile memories, nano-random access memory (NRAM) has advantages of small program current and high endurance compared with resistive RAM (ReRAM) and phase-change RAM (PRAM). This work comprehensively investigates NRAM set and reset program characteristics by measuring a 116 nm 4 Mbit NRAM cell array. Specifically, reset is found more dependent on reset voltage than reset current. Next, NRAM set and reset bit error rates (BERs) have less significant reduction compared with the increased ratio of set and reset pulse widths. The reset BER can also be reduced by applying multiple reset pulses. Moreover, 108 write cycles are measured on 256 bytes NRAM cells, no wear-out or broken cell is found. Finally, the program characteristics of two verify-reset schemes are compared. The maximum verify-reset voltage can be reduced by increasing the number of reset pulses.

Design Methodology for Highly Reliable, High Performance ReRAM and 3-Bit/Cell MLC NAND Flash Solid-State Storage

This paper proposes design methodology for highly reliable, high performance ReRAM and 3-bit/cell multi-level cell (MLC) NAND flash solid-state storage. Six techniques, calibrated RRef (CR), flexible RRef (FR), adaptive asymmetric coding (AAC), verify trials reduction (VTR), bits/cell optimization (BCO), and balanced RAID-5/6 are proposed. CR, FR, AAC, and VTR are for ReRAM. CR and FR change the read-reference resistance (RRef) to reduce the BER. AAC first increases the population of Set and then Reset. The BER reduction with FR and AAC is 69 and 78% with 60 and 75% asymmetry, respectively. In VTR, by changing the number of acceptable bit-errors, the total Reset time is reduced by 97% at maximum with small ECC calculation overhead. The reliability of 3-bit/cell MLC NAND flash memory is improved by BCO and balanced RAID-5/6. BCO reallocates 3-bit/cell MLC to 2-bit/cell MLC and single-level cell (SLC) and the write/erase cycle increases by over 22-times. Balanced RAID-5/6 evenly allocates upper/middle/lower pages to a stripe to reduce the RAID failure rate by 98%.