Shogo Hachiya

Application Driven SCM and NAND Flash Hybrid SSD Design for Data-Centric Computing System

In order to efficiently store, retrieve and process big data, the data-centric computing paradigm is adopted and an application-driven storage class memory (SCM)/NAND flash hybrid solid-state drive (SSD) is designed. SSD data management algorithms minimize data movement inside the storage system and the SSD system design parameter, SCM/NAND capacity ratio, is chosen depending on the application. Design guidelines are proposed, based on the evaluation of three SCM/NAND flash hybrid SSDs with: (1) write-back (WB) cache, (2) write-optimized data management (WO-DM) and (3) read-write balanced data management (RWB-DM) algorithms. The WO-DM algorithm achieves the highest SSD performance for write-intensive applications, whereas RWB-DM is most appropriate for read-hot (frequently accessed)-random workloads. As long as the workload is not read-cold-sequential or write-cold-sequential, adding SCM to the NAND SSD system is cost-effective to boost performance. Less than 10% SCM/NAND capacity ratios provides 10x speed, compared to the NAND flash-only SSD.

TLC/MLC NAND Flash Mix-and-Match Design with Exchangeable Storage Array

Shogo Hachiya, Koh Johguchi, Kousuke Miyaji and Ken Takeuchi 1 Chuo Univ. 1-13-27 Kasuga, Bunkyo-ku, Tokyo 112-8551, Japan, 2 Shinshu Univ. E-mail: johguchi@takeuchi-lab.org Abstract This paper proposes TLC/MLC NAND flash mix-and-match design method for exchangeable storage array. The proposed Round-Robin frozen data collection achieves 56% higher write performance and 29% write energy reduction compared with the conventional MLC only SSD. SSD card exchange method is also presented to realize sustainable and flexible storage arrays.

7.7 Enterprise-grade 6x fast read and 5x highly reliable SSD with TLC NAND-flash memory for big-data storage

An enterprise-grade SSD with TLC (3b/cell) NAND Flash is presented with three techniques that achieve high speed and high reliability. Quick low-density parity-check (LDPC) reduces the read latency of 1Xnm TLC NAND Flash SSD by 83%. Dynamic VTH optimization and auto data recovery reduce the NAND Flash bit-error rate (BER) by 80% and 18%, respectively. These techniques can be implemented in the SSD controller without circuit overhead. No modification is required to the TLC NAND flash.

Hybrid triple-level-cell/multi-level-cell NAND flash storage array with chip exchangeable method

This paper proposes a mix-and-match design method for triple level cell (TLC)/multi level cell (MLC) NAND flash hybrid and exchangeable storage arrays. A TLC-NAND flash provides an low cost and high capacity memory solution. However the reliability and access latency of TLC NAND flash are degraded from MLC NAND flash. Additionally, the block unit write is preferable for TLC NAND flash since the write order is complicated due to narrow data margin and write disturbance. The proposed solution combines TLC and MLC NAND flash memories for a storage array. To reduce access to TLC NAND flash, the stored data is screened and only the static frozen data are stored into TLC NAND flash with a Round-Robin frozen data collection algorithm (RR-FDCA). Furthermore, the proposed chip exchanging method extends the solid-state drive (SSD) lifetime without system suspending. As a result, in spite of moderate characteristics of TLC NAND flash, the proposed storage array can achieve 29% write energy saving and 56% write performance enhancement with 17% cost reduction, compared with the conventional MLC-only SSD.

Reliability enhancement of 1Xnm TLC for cold flash and millennium memories

Endurance and retention are measured in 1Xnm Triple Level Cell (TLC) NAND and the flexible nLC scheme (flex-nLC) is proposed to improve reliability. This method enables the use of lowest-cost TLC NAND as is, in long term storage applications such as cold flash and digital archive: millennium memory, which have 20 and 1000 years retention, respectively.

0.6 V operation, 26% smaller voltage ripple, 9% energy efficient boost converter with adaptively optimized comparator bias-current for ReRAM program in low power IoT embedded applications

The Internet of Things (IoT) applies the sensors and MCUs on various machines, devices and equipment, and connect them through internet. The emerging non-volatile memory, Resistive Random Access Memory (ReRAM) is suitable for the sensor data storage because of the low voltage and low power program operation. In this paper, the proposed 0. 6 V operation, 0.27 mm2 die size boost converter is demonstrated to achieve low ReRAM program voltage ripple (Cripple) and high energy efficiency (η), simultaneously, by using the 2 μA to 8 μA adaptive comparator current (ICMP). In detail, for one ReRAM cell program, the proposed boost converter reduces VRIPPLE by 26% compared with the conventional boost converter with fixed 2 μA small ICMP. For 16 ReRAM cells program, the proposed boost converter improves 8.9% energy efficiency compared with the conventional boost converter with fixed 8 μA large ICMP.

Carbon nanotube memory cell array program error analysis and tradeoff between reset voltage and verify pulses

In emerging non-volatile memories, nano-random access memory (NRAM) has advantages of small program current and high endurance compared with resistive RAM (ReRAM) and phase-change RAM (PRAM). This work comprehensively investigates NRAM set and reset program characteristics by measuring a 116 nm 4 Mbit NRAM cell array. Specifically, reset is found more dependent on reset voltage than reset current. Next, NRAM set and reset bit error rates (BERs) have less significant reduction compared with the increased ratio of set and reset pulse widths. The reset BER can also be reduced by applying multiple reset pulses. Moreover, 108 write cycles are measured on 256 bytes NRAM cells, no wear-out or broken cell is found. Finally, the program characteristics of two verify-reset schemes are compared. The maximum verify-reset voltage can be reduced by increasing the number of reset pulses.

Design guidelines of storage class memory/flash hybrid solid-state drive considering system architecture, algorithm and workload characteristic

Solid-state drives (SSDs), composed of NAND flash memories, are replacing hard disk drives (HDDs) rapidly. In addition, storage class memories (SCMs) bridge the bandwidth gap between DRAM and NAND flash, thus introducing SCM to SSD further improves the solid storage performance. Different from schemes that use SCM to store file system metadata or logical to physical mapping tables, two architectures 1) use SCM as a write-back non-volatile memory (NVM) based cache, 2) use SCM as a storage device are presented in this paper. Since SCM chip latency varies due to memory device and circuit design, three SSD data management algorithms are evaluated under five SCM chip design scenarios to provide useful design guidelines of SCM/NAND flash hybrid SSD. SCM interface and capacity requirement are also analyzed. From the experimental results, less than 10% of the SCM/NAND flash capacity ratio is enough for SCM chips with 500 ns read and 5 μs write latency to boost NAND flash-only SSD speed by over 10 times when workloads own high IO skew1.

0.6–1.0 V operation set/reset voltage (3 V) generator for three-dimensional integrated resistive random access memory and NAND flash hybrid solid-state drive

A 0.6–1.0 V, 25.9 mm2 boost converter is proposed to generate resistive random access memory (ReRAM) write (set/reset) voltage for three-dimensional (3D) integrated ReRAM and NAND flash hybrid solid-state drive (SSD). The proposed boost converter uses an integrated area-efficient V BUF generation circuit to obtain short ReRAM sector write time, small circuit size, and small energy consumption simultaneously. In specific, the proposed boost converter reduces ReRAM sector write time by 65% compared with a conventional one-stage boost converter (Conventional 1) which uses 1.0 V operating voltage. On the other hand, by using the same ReRAM sector write time, the proposed boost converter reduces 49% circuit area and 46% energy consumption compared with a conventional two-stage boost converter (Conventional 2). In addition, by using the proposed boost converter, the operating voltage, V DD, can be reduced to 0.6 V. The lowest 159 nJ energy consumption can be obtained when V DD is 0.7 V.

Comprehensive comparison of 3D-TSV integrated solid-state drives (SSDs) with storage class memory and NAND flash memory

Three dimensional (3D) through-silicon via (TSV) integrated solid-state drive (SSD) with storage class memory (SCM) has been proposed as a candidate for the next generation storage drive. The 3D-TSV SSD has advantages of fast speed, low energy consumption, and high endurance [1-3]. This paper comprehensively compares the characteristics of SSDs with and without 3D-TSV. First, different data management algorithms are explained by using SSDs with different memory devices, respectively. Moreover, their write performances, energies and required minimum I/O data rates are simulated and compared. Specifically, the all SCM SSD increases write performance by 295 times compared with MLC only NAND flash SSD, due to the high SCM performance. As for the SCM/MLC NAND hybrid SSD, the write energy reduces 68% by applying 3D-TSV. In addition, only the all SCM SSD needs higher I/O data rate than the conventional 400 MBytes/s NAND flash I/O data rate.