Tillmann Krauss

Reconfigurable CMOS with undoped silicon nanowire midgap Schottky-barrier FETs

In this paper we report on a newly developed multi-gate nanowire-field-effect device (NWFET) in which the transistor type (i.e. PMOS and NMOS) is freely selectable by the application of a control-voltage. This significantly adds to flexibility in design of integrated circuits and their fabrication, respectively. We will show, that the use of midgap Schottky-barrier source and drain contacts are the key enabler for this device concept to be functional. A fully functional freely configurable CMOS-NWFET inverter circuit is presented, demonstrating the capability of this SOI technology platform. All this makes the presented NWFET-technology suitable for the fabrication multi-purpose devices for many applications. HighlightsÂ? Virtually dopant-free CMOS multi-gate silicon-nanowire FET SOI technology. Â? Midgap Schottky-barrier source/drain enabling carrier tunneling. Â? Use of Schottky-barriers provides low source/drain leakage. Â? Asymmetric workfunction metal not suitable for NWFET technology. Â? Voltage selectable NWFET types add to flexibility in circuit design.

Dopant-free CMOS: A new device concept

In this paper we report on a newly developed multigate nanowire (NW) based field-effect device (NWFET) where the transistor type is freely selectable by the application of a control-voltage, adding to design flexibility in integrated circuit fabrication. Moreover, the midgap Schottky-barrier source and drain contacts of the NWFET make it feasible for the usa in high temperature environments, since the devices posses both stability against high temperatures and low OFF-state current at the same time. This makes the presented NWFET a multi-purpose device for many specific circuit applications.

Dopant-independent and voltage-selectable silicon-nanowire-CMOS technology for reconfigurable logic applications

In this paper, we report on the fabrication and characterization of a novel voltage-selectable (VS) nanowire (NW) CMOS technology suitable to extend the flexibility in circuit design and reconfigurable logic applications. Silicon NW-structures with Schottky-S/D-junctions on silicon-on-insulator (SOI) substrate are used to realize dopant-independent unipolar CMOS-like transistors. A selection of the device type (PMOS or NMOS) is performed by application of an appropriate back-gate bias. The versatile programming capability of this approach is demonstrated in a VS-NW-CMOS inverter set-up.

On the Physical Behavior of Cryogenic IV and III–V Schottky Barrier MOSFET Devices

The physical influence of temperature down to the cryogenic regime is analyzed in a comprehensive study and the comparison of IV and III–V Schottky barrier (SB) double-gate MOSFETs. The exploration is done using the Synopsys TCAD Sentaurus device simulator and first benchmarked with experimental data. The important device physics of both SB-MOSFETs and conventional MOSFETs are reviewed. The impact of temperature on device performance down to the liquid-nitrogen regime is then explored. We find reduced drive currents in SB-MOSFETs fabricated on small effective mass materials and that SB lowering can significantly improve SB-MOSFETs, especially at low temperatures.

CMOS without doping: Midgap Schottky-barrier nanowire field-effect-transistors for high-temperature applications

In this paper we report on a newly developed nanowire based field-effect device-architecture (NWFET) that can be used in high temperature environments. Our devices posess both high temperature stability and low OFF-state current. By changes in source/drain bias-polarity the electrical properties of the NW-devices can be tuned, whether the lowest possible leakage current, or maximum output current is desirable in a specific application.

Electrically reconfigurable dual metal-gate planar field-effect transistor for dopant-free CMOS

In this paper, we demonstrate by simulation the feasibility of electrostatically doped and therefore reconfigurable planar field-effect-transistor structure which is based on our already fabricated and published Si-nanowire devices. The technological cornerstones for this dual-gated general purpose FET contain Schottky S/D junctions on a silicon-on-insulator substrate. The transistor type, i.e. n-type or p-type FET, is electrically selectable on the fly by applying an appropriate control-gate voltage which significantly increases the versatility and flexibility in the design of digital integrated circuits.

Fabrication and simulation of electrically reconfigurable dual metal-gate planar field-effect transistors for dopant-free CMOS

In this paper, we illustrate by simulation and extend our previous work by demonstration of fabricated devices of electrostatically doped, reconfigurable planar field-effect-transistors with dual work function metal gates. The technological cornerstones for this dual-gated general purpose FET contain Schottky S/D junctions on a silicon-on-insulator substrate. The transistor type, i.e. n-type or p-type FET, is electrically selectable in operation by applying a control-gate voltage which significantly increases the versatility and flexibility in the design of digital integrated circuits.

Simulation framework for barrier lowering in Schottky barrier MOSFETs

In this paper we present a simulation framework to account for the Schottky barrier lowering models in SB-MOSFETs within the Synopsys TCAD Sentaurus tool-chain. The improved Schottky barrier lowering model for field emission is considered. A strategy to extract the different current components and thus predict accurately the on- and off-current regions are adressed.

An electrostatically doped planar device concept

In this paper, we propose and demonstrate by simulation an electrostatically doped and therefore voltage-programmable planar field-effect-transistor (FET) structure which is based on our results of already published Si-nanowire (SiNW) devices. The key technology for this dual-gated general purpose FET contain Schottky S/D junctions on a silicon-on-insulator (SOI) platform. The desired transistor type, i.e. NFET or PFET, is selectable on the fly by applying an appropriate control-voltage which significantly enhances flexibility in design of integrated circuits.

Simulation and experimental verification: Dopant-free Si-nanowire CMOS technology on silicon-on-insulator material

In CMOS technology, NMOS- and PMOS-FETs are hardware defined by choosing the appropriate doping of source (S) and drain (D) junctions with respect to the substrate. However, in this work we report on a novel CMOS multi-gate (MG) nanowire field-effect transistor (NWFET) architecture on silicon-on-insulator (SOI) material which is virtually free of doping. The MG-NWFETs are originally ambipolar nanowire devices with midgap Schottky-barriers serving as S/D contacts. A tri-gate structure is used as front-gate for current control across the NWFET whereas a planar back-gate is used to select the desired unipolar device type (i.e. NMOS or PMOS) via field-induced accumulation of electrons or holes, respectively. Both, logic and memory devices can be realized with the same simple nanowire structure. By means of 2D and 3D device simulation and subsequent experimental verification the potential of this novel reconfigurable device and circuit architecture will be demonstrated.