Frank Wessely

Transfer-free fabrication of graphene transistors

The authors invented a method to fabricate graphene transistors on oxidized silicon wafers without the need to transfer graphene layers. To stimulate the growth of graphene layers on oxidized silicon, a catalyst system of nanometer thin aluminum/nickel double layer is used. This catalyst system is structured via liftoff before the wafer enters the catalytic chemical vapor deposition (CCVD) chamber. In the subsequent methane-based growth process, monolayer graphene field-effect transistors and bilayer graphene field-effect transistors are realized directly on oxidized silicon substrate, whereby the number of stacked graphene layers is determined by the selected CCVD process parameters, e.g., temperature and gas mixture. Subsequently, Raman spectroscopy is performed within the channel region in between the catalytic areas and the Raman spectra of five-layer, bilayer, and monolayer graphene confirm the existence of graphene grown by this silicon-compatible, transfer-free and in situ fabrication approach. The...

Reconfigurable CMOS with undoped silicon nanowire midgap Schottky-barrier FETs

In this paper we report on a newly developed multi-gate nanowire-field-effect device (NWFET) in which the transistor type (i.e. PMOS and NMOS) is freely selectable by the application of a control-voltage. This significantly adds to flexibility in design of integrated circuits and their fabrication, respectively. We will show, that the use of midgap Schottky-barrier source and drain contacts are the key enabler for this device concept to be functional. A fully functional freely configurable CMOS-NWFET inverter circuit is presented, demonstrating the capability of this SOI technology platform. All this makes the presented NWFET-technology suitable for the fabrication multi-purpose devices for many applications. HighlightsÂ? Virtually dopant-free CMOS multi-gate silicon-nanowire FET SOI technology. Â? Midgap Schottky-barrier source/drain enabling carrier tunneling. Â? Use of Schottky-barriers provides low source/drain leakage. Â? Asymmetric workfunction metal not suitable for NWFET technology. Â? Voltage selectable NWFET types add to flexibility in circuit design.

Carbon Nanotube Transistor Fabrication Assisted by Topographical and Conductive Atomic Force Microscopy

In this work, fully functional carbon nanotube field-effect transistors (CNT-FETs) have been fabricated using a simple and inexpensive process including in-situ chemical vapor deposition (CVD) growth of the nanotubes. The temperature used is 900 °C and the catalyst layer is nickel on aluminum. Simultaneously, the catalyst metal areas are used as source/drain electrodes. The CNT-FET fabrication is compatible with conventional complementary metal oxide semiconductor (CMOS) technology. For process optimization, every major process step is controlled by atomic force microscopy (AFM). The nondestructive AFM technique provides both a complete overview of the structures as well as the detailed geometrical properties of the nanotubes. We have also fabricated CNT-FET test structures in which the source/drain electrodes have a direct conductive path to the substrate, in order to perform electrical measurements at the nanoscale by conductive AFM (C-AFM). In this way, we obtain current images of the structures and the electrical characteristics of each individual nanotube can be measured.

Dopant-free CMOS: A new device concept

In this paper we report on a newly developed multigate nanowire (NW) based field-effect device (NWFET) where the transistor type is freely selectable by the application of a control-voltage, adding to design flexibility in integrated circuit fabrication. Moreover, the midgap Schottky-barrier source and drain contacts of the NWFET make it feasible for the usa in high temperature environments, since the devices posses both stability against high temperatures and low OFF-state current at the same time. This makes the presented NWFET a multi-purpose device for many specific circuit applications.

CVD assisted fabrication of graphene layers for field effect device fabrication

In this paper, we report on the fabrication and characterization of graphene layers for graphene field effect devices. After the graphene layers are fabricated by means of chemical vapor deposition using a methane feedstock, the band gap is engineered confining the lateral dimensions of graphene in order to obtain graphene nanoribbons. Contacting the graphene nanoribbons with appropriate metallic materials will lead to field effect devices suitable for various applications.

Dopant-independent and voltage-selectable silicon-nanowire-CMOS technology for reconfigurable logic applications

In this paper, we report on the fabrication and characterization of a novel voltage-selectable (VS) nanowire (NW) CMOS technology suitable to extend the flexibility in circuit design and reconfigurable logic applications. Silicon NW-structures with Schottky-S/D-junctions on silicon-on-insulator (SOI) substrate are used to realize dopant-independent unipolar CMOS-like transistors. A selection of the device type (PMOS or NMOS) is performed by application of an appropriate back-gate bias. The versatile programming capability of this approach is demonstrated in a VS-NW-CMOS inverter set-up.

In-Situ CCVD Grown Bilayer Graphene Transistor

In this paper we report on a novel method to fabricate graphene transistors directly on oxidized silicon wafers without the need to transfer graphene. By means of catalytic chemical vapor deposition (CCVD) the in-situ grown monolayer graphene field-effect transistors (MoLGFETs) and bilayer graphene field-effect transistors (BiLGFETs) are realized directly on oxidized silicon substrate. In-situ CCVD grown MoLGFETs exhibit the expected Dirac point together with the typical low on/off-current ratios of 16. In addition, however, in-situ CCVD grown BiLGFETs possess unipolar p-type device characteristics with an extremely high on/off-current ratio up to 1x10 7 exceeding previously reported values by several orders of magnitude. With this novel fabrication method hundreds of large scale in-situ CCVD grown graphene FETs are realized simultaneously on one 2’’ wafer. Besides the excellent device characteristics, the complete CCVD fabrication process is silicon CMOS compatible. This will allow a simple and low-cost integration of graphene devices for nanoelectronic applications in a hybrid silicon CMOS environment.

In-Situ CCVD Grown Graphene Transistors with Ultra-high On/Off-Current Ratio in Silicon CMOS Compatible Processing

We invented a novel method to fabricate graphene transistors on oxidized silicon wafers without the need to transfer graphene layers. By means of catalytic chemical vapor deposition (CCVD) the in-situ grown monolayer graphene field-effect transistors (MoLGFETs) and bilayer graphene transistors (BiLGFETs) are realized directly on oxidized silicon substrate, whereby the number of stacked graphene layers is determined by the selected CCVD process parameters. In-situ grown MoLGFETs exhibit the expected Dirac point together with the typical low on/off-current ratios between 16 (hole conduction) and 8 (electron conduction), respectively. In contrast, our BiLGFETs possess unipolar p-type device characteristics with an extremely high on/off-current ratio up to 1E7 exceeding previously reported values by several orders of magnitude. We explain the improved device characteristics by a combination of effects, in particular graphene-substrate interactions, hydrogen doping and Schottky-barrier effects at the source/drain contacts as well. Besides the excellent device characteristics, the complete CCVD fabrication process is silicon CMOS compatible. This will allow the usage of BiLGFETs for digital applications in a hybrid silicon CMOS environment.

Nanoelectronics: From silicon to graphene

In the future of nanoelectronics, the use of pure silicon based devices will not be possible anymore since the limit of silicon are already reached. Carbon seems to be a great alternative to build high performance electronic devices. Carbon nanotube field-effect transistors can be used as active device in integrated circuits, as memory cell in numerous applications. More recently, graphene-based transistors are emerging as another potential candidate to extend and eventually replace the traditional planar MOSFET.

CMOS without doping: Midgap Schottky-barrier nanowire field-effect-transistors for high-temperature applications

In this paper we report on a newly developed nanowire based field-effect device-architecture (NWFET) that can be used in high temperature environments. Our devices posess both high temperature stability and low OFF-state current. By changes in source/drain bias-polarity the electrical properties of the NW-devices can be tuned, whether the lowest possible leakage current, or maximum output current is desirable in a specific application.