Ralf Endres

Complementary metal oxide semiconductor integration of epitaxial Gd2O3

In this paper, epitaxial gadolinium oxide (Gd2O3) is reviewed as a potential high-K gate dielectric, both “as deposited” by molecular beam epitaxy as well as after integration into complementary metal oxide semiconductor (CMOS) processes. The material shows promising intrinsic properties, meeting critical ITRS targets for leakage current densities even at subnanometer equivalent oxide thicknesses. These epitaxial oxides can be integrated into a CMOS platform by a “gentle” replacement gate process. While high temperature processing potentially degrades the material, a route toward thermally stable epitaxial Gd2O3 gate dielectrics is explored by carefully controlling the annealing conditions.

Dopant free multi-gate silicon nanowire CMOS-inverter on SOI substrate

In this work, we report on the fabrication and characterization of voltage-programmable (VP) nanowire (NW) field-effect-transistor (FET) devices suitable to extend the flexibility in circuit design, i.e. of reconfigurable logic. Ultra-thin silicon NW-structures with mid-gap Schottky S/D junctions on silicon-on-insulator (SOI) substrate have been fabricated as dopant free unipolar CMOS transistors. The desired device type, i.e. NMOS or PMOS, is selected by applying an appropriate back-gate bias voltage. The programming capability of the devices fabricated using this approach is demonstrated experimentally using a VP-NW-CMOS inverter circuit on a multi-SOI-like set-up.

Damascene metal gate technology for damage-free gate-last high-k process integration

In this work, we present MOS capacitors and MOS transistors with a crystalline gadolinium oxide (Gd<inf>2</inf>O<inf>3</inf>) gate dielectric and metal gate electrode (titanium nitride) fabricated in a replacement gate process. Initial results on ALD-TiN/Gd<inf>2</inf>O<inf>3</inf>/Si gate stacks on p- and n-substrates with equivalent oxide thicknesses (EOT) of 3.0nm and 1.5nm, respectively, are presented in this work.

Scaling the Damascene-Metal-Gate integration process via electron beam lithography

Damascene-Metal-Gate technology gives rise to the implementation of crystalline gate dielectrics into modern MOS devices. Evaluation of the scalability of this fabrication process is important for a subsequent use in industrial-scale fabrication. Devices were processed on ultrathin Unibond SOI-Wafers. A high-K specially designed layout was patterned onto the substrates via mix and match electron-beam / UV lithography. A gate length of ∼100nm was chosen for a first approach. Reactive ion etching was performed for dummy gate and active area formation. Subsequently the surface was planarized via chemical mechanical planarization (CMP). In the following the dummy gate was removed, and in one case replaced with molecular beam epitaxially grown crystalline gadolinium oxide (Gd2O3) and on the other case with thermally grown SiO2 as reference material. Palladium was used as source/drain- and gate-metallisation. Atomic force microscopy and scanning electron microscopy were carried out for process monitoring. Especially the dummy gate formation, subsequent CMP and cleaning processes, as well as the dummy gate removal and the conformity of the replacement gate stack are of particular interest.