Timothy G. Dunham

TCAD development for lithography resolution enhancement

Advances in lithography have contributed significantly to the advancement of the integrated circuit technology. While nonoptical next-generation lithography (NGL) solutions are being developed, optical lithography continues to be the workhorse for high-throughput very-large-scale integrated (VLSI) lithography. Extending optical lithography to the resolution levels necessary to support today’s aggressive product road maps increasingly requires the use of resolution-enhancement techniques. This paper presents an overview of several resolution-enhancement techniques being developed and implemented in IBM for its leading-edge CMOS logic and memory products.

Optical rule checking for proximity-corrected mask shapes

Optical Rule Checking (ORC) is an important vehicle to predict the failure of wafer shapes due to the process proximity effects. Optical Proximity Correction (OPC) if not aided by ORC may cause severe failures affecting the yield in manufacturing. However, it is fairly complicated to do ORC on mask shapes that are pre-corrected either by rules-based or by model-based OPC. ORC is also a good tool to capture the problems that may occur at multi-layer interactions. We present a methodology to use both geometric directives and limited optical simulation to detect potential failures using ORC. We extend our methodology to multi-layer interactions. In case of multi-layer ORC, we present several approaches that deal with how to judiciously mix the geometric directives and the optical simulations for different layers. We show the ORC can help us design better rules for OPC.

ASIC data preparation management for OPC

ASIC layout data, which can be large and typically with little hierarchy, can prove challenging for complex optical proximity correction (OPC) operations. Thoughtful coordination between the ASIC library designers and the OPC code developers in terms of design and execution methodologies can result in large savings in run time and additional hierarchy flattening with little or no impact to the library layout density. We will show results from such a collaboration on IBM