Howard S. Landis

Integration of chemical-mechanical polishing into CMOS integrated circuit manufacturing

Abstract Planarization by chemical-mechanical polishing (CMP) has been exploited by IBM in the development and manufacture of CMOS products since 1985. Among the products that use this technology are the 4-Mbit DRAM (which uses polysilicon, oxide, tungsten-line and tungsten-stud planarization) and its logic family (which uses four oxide and four tungsten-stud planarization steps). CMP is also used in the planarization of oxide shallow isolation trenches, as in the 16-Mbit DRAM. Reduced sensitivity to many types of defects is possible with CMP. A wafer that is truly flat is easier to clean, eliminates step coverage concerns, provides for better photolithographic and dry etch yields, and generally minimizes complications from prior level structures. Oxide CMP reduces sensitivity to certain pre-existing defects, such as crystalline inclusions or foreign material in an interlevel dielectric. Metal CMP can reduce the incidence of intralevel shorts relative to conventional RIE processing. Random defects associated with CMP, such as slurry residues and mechanical damage, are controlled by careful optimization of the post-polish clean and of the polish process itself. Systematic defects, such as incomplete planarization over very large structures, are controlled by process optimization and prudent design limitations. These include such things as constraints on the image size, the distance between images, and/or the local pattern density. Since its introduction in the 4-Mbit DRAM, there has been a steady increase in the use of chemical-mechanical polishing in IBM CMOS products. The number of steps, processes and materials polished continue to rise, both in current and planned future products. Individual applications range from the simple removal of back-side films to complex insulator or metal planarization requiring high removal uniformity. The process tolerances delivered by CMP have decreased faster than image size, even in the face of dramatic increases in circuit and layout complexity. CMP tools are installed in IBM semiconductor manufacturing and development sites worldwide. Chemical-mechanical polish processes and applications provide unique leverage to IBM products, and are a crucial part of both current and planned IBM CMOS technologies.

Pattern Density Methodology Using IBM Foundry Technologies

An overview of important pattern density requirements and tradeoffs for advanced RF, analog and digital technologies is presented. This paper reviews process sensitivities to pattern density, the advantage of pattern density compliant designs, performance and modeling considerations, and presents methods of detecting and enhancing pattern density deficiencies to improve overall manufacturability.

Effects of photoresist foreshortening on an advanced Ti/AlCu/Ti metallurgy and W interconnect technology

Competitive technology ground rules for BEOL (Back end of Line) interconnects have been shrinking aggressively. Extending the life of existing tool sets and manufacturing processes for these new aggressive technologies is required to make these newer technologes cost competitive. This paper describes the early process transfer phase of a technology installation into a manufacturing. The effects of photolithography induced metal line end shortening foreshortening) can have a significant impact on the etched Ti/AlCu/Ti/TiN metal lines (Figure 1). This defect observed after metal etch is directly attributed to foreshortening of the photoresist lines. When a tungsten contact (interconnect) is not fully covered by a resist line during the metal etch and subsequent chromic phosphoric clean operation, attack of the Ti/AlCu/Ti metallurgy occurred. The metal defect resulted in test yield loss due to open metal line and high via resistance which impacted wafer final test yield. This defect was found to impact single metal to via interfaces within small via chain defect monitors which lead to serious reliability concerns due to the low level of detectability for this problem on products.