Ting-Pu Tai

Efficiently Performing Yield Enhancements by Identifying Dominant Physical Root Cause from Test Fail Data

Yield enhancements in the manufacturing process today require an expensive, long and tedious physical failure analysis process to identify the root cause. In this paper we present Axiom, a new technique geared towards efficiently identifying a single dominant defect mechanism (for example in an excursion wafer) by analyzing fail data collected from the production test environment. Axiom utilizes statistical hypothesis testing in a novel way to analyze logic diagnosis data along with information on physical features in the design layout and reliably identify the dominant cause for yield loss. This new methodology was validated by applying it to a single excursion wafer produced on a 90 nm process, in which the dominant failing physical feature was correctly identified.

Faster defect localization in nanometer technology based on defective cell diagnosis

In this paper we present practical techniques that enable diagnosis of defective library cells in a failing die. Our technique can handle large industrial designs and practical situations like compressed test patterns with multiple exercising conditions per pattern and sequence dependent defects. Being able to accurately differentiate between cell-internal and interconnect defects leads to a faster root cause failure analysis at a reduced cost. This capability was applied on an AMD graphics chip using 90 nm at TSMC. In all of the failing dies that underwent physical failure analysis, the defective library cell identified by diagnosis was verified to be correct by failure analysis. Currently this capability is successfully used to diagnose another design using TSMCs 65 nm technology.

Scan Chain Diagnosis by Adaptive Signal Profiling with Manufacturing ATPG Patterns

In the past, software based scan chain defect diagnosis can be roughly classified into two categories (1) model-based algorithms, and (2) data-driven algorithms. In this paper we first analyze the advantages and disadvantages of each category of the chain diagnosis algorithms. Next, an adaptive signal profiling algorithm that can use manufacturing ATPG scan patterns is proposed for scan chain diagnosis. Finally, several case studies and their PFA results are presented to validate the accuracy and effectiveness of the proposed algorithm.

Test cycle power optimization for scan-based designs

Extraordinary power consumption during the scan test may inadvertently cause a functional good die to fail. This paper proposes a peak power reduction algorithm for the scan test which considers both the shift cycles and capture cycles simultaneously to limit the peak power of all test cycles during the test generation. In addition, the analysis also recommends the types of circuit structures that are more suitable to add test logic for maximum power reduction with the minimum test cost. The proposed methodology is highly efficient and can be applied to large industrial designs.

Automotive semiconductor test

Meeting the quality and reliability requirements of the ISO 26262 and other automotive electronics standards will only become more difficult as device sizes and complexities continue to grow. New advanced test technologies such as cell-aware ATPG, hybrid compression / logic BIST / memory BIST and diagnosis-driven yield analysis with RCD provide some key building blocks towards ensuring compliance to the new standards. Adoption of these and other advanced test capabilities will not only improve the ability of semiconductor manufacturers to achieve necessary quality and reliability metrics, but will also help to further differentiate their products by delivering embedded test capabilities that can be leveraged by their customers at the system level and in the field.

Diagnosing timing related cell internal defects for FinFET technology

The semiconductor industry is encountering an increasing number of front-end-of-line defects in the advanced FinFET technology nodes due to extremely small feature size and complex manufacturing processes required for FinFET transistors. Traditional delay diagnosis algorithm has a limited support for cell internal timing related failures based on transition delay faults, and tends to provide a large suspect list. It cannot provide the precise defect location inside the cell that is necessary for effective physical failure analysis and statistical yield learning. In this work, we present a new cell-aware delay diagnosis algorithm, based on accurate delay fault models derived by analog simulation, which can pinpoint the defect location within a cell for various timing related cell internal defects. Preliminary results for real silicon failures show that significant diagnosis resolution improvement can be achieved by the proposed method.

Case study of scan chain diagnosis and PFA on a low yield wafer

In this poster, we share our industrial experiences on running chain diagnosis and PFA (Physical Failure Analysis) on a wafer that suffered from low yield. In addition, case study on PFA will be illustrated.

Customized Algorithms for High Performance Memory Test in Advanced Technology Node

Chip quality is becoming more difficult to maintain as the process geometry shrinks. Not only is design complexity higher, but new defect types cause DPM (defects per million) to increase. At the same time, the amount of embedded memory in many applications continues to grow, making memory testing a key factor in maintaining low cost and high quality in IC manufacturing. While commercial EDA tools are keeping pace with the need for greater test flow automation, new test algorithms are also needed to minimize the rate of field returns at advanced technology nodes. This paper describes how ASIC vendors can develop customized memory test algorithms to enhance their overall IC testing strategy.