Tobias Mono

A 0.13 /spl mu/m CMOS platform with Cu/low-k interconnects for system on chip applications

We describe an advanced 0.13 /spl mu/m CMOS technology platform optimized for density, performance, low power and analog/mixed signal applications. Up to 8 levels of copper interconnect with the industrys first true low-k dielectric (SiLK, k=2.7) (Goldblatt et al., 2000) result in superior interconnect performance at aggressive pitches. A 2.28 /spl mu/m/sup 2/ SRAM cell is manufactured with high yield by introducing elongated local interconnects on the contact level without increasing process complexity. Trench based embedded DRAM is offered for large area memory. Modular analog devices as well as passive components like resistors, MIM capacitors and intrinsic inductors are integrated.

Overlay considerations for 300-mm lithography

Generally, the potential impact of systematical overlay errors on 300mm wafers is much larger than on 200mm wafers. Process problems which are merely identified as minor edge yield detractors on 200mm wafers, can evolve as major roadblocks for 300mm lithography. Therefore, it is commonly believed that achieving product overlay specifications on 300mm wafers is much more difficult than on 200mm wafers. Based on recent results on high volume 300mm DRAM manufacturing, it is shown that in reality this assumption does not hold. By optimizing the process, overlay results can be achieved which are comparable to the 200mm reference process. However, the influence of non-lithographic processes on the overlay performance becomes much more critical. Based on examples for specific overlay signatures, the influence of several processes on the overlay characteristics of 300mm wafers is demonstrated. Thus, process setup and process changes need to be analyzed monitored much more carefully. Any process variations affecting wafer related overlay have to be observed carefully. Fast reaction times are critical to avoid major yield loss. As the semiconductor industry converts to 300mm technology, lithographers have to focus more than ever on process integration aspects.

OPC for logic and embedded applications: the reverse approach

In this paper we demonstrate a method of correcting optical proximity effects, which is specifically tailored for logic applications. Since the lithographic process window for printing logic features is predominantly determined by isolated lines, it makes sense to optimize the exposure conditions for isolated features, and then correct more nested features. As a result, the common process window is improved. Another benefit from this technique is that a smaller fraction of structures has to be corrected, thus reducing computation time and data volume. This makes this method useful also for logic application with embedded dense features.