Junichi Yamada

NV-SRAM: a nonvolatile SRAM with backup ferroelectric capacitors

This paper demonstrates new circuit technologies that enable a 0.25-/spl mu/m ASIC SRAM macro to be nonvolatile with only a 17% cell-area overhead. New capacitor-on-metal/via-stacked-plug process technologies permit a nonvolatile SRAM (NV-SRAM) cell to consist of a six-transistor ASIC SRAM cell and two backup ferroelectric capacitors stacked over the SRAM portion. READ and WRITE operations in this NV-SRAM cell are very similar to those of a standard SRAM, and this NV-SRAM shares almost all the circuit properties of a standard SRAM. Because each memory cell can perform STORE and RECALL individually, both can execute massive-parallel operations. A V/sub dd//2 plate-line architecture makes READ/WRITE fatigue negligible. A 512-byte test chip was successfully fabricated to show compatibility with ASIC technologies.

A 128 kb FeRAM macro for a contact/contactless smart card microcontroller

For contact/contactless smart-card applications, a ferroelectric RAM (FeRAM) macro must operate with supply voltages ranging from 2.7 V to 5.5 V, as standardized by ISO, and have endurance of more than 10/sup 8/ write/read cycles and memory size flexible from 32 kb to 128 kb. In addition, for contactless smart card applications, low current consumption is essential. This macro meets these requirements using: (1) 3-metal process capacitor-on-metal/via-stacked-plug (CMVP) memory cell; (2) voltage regulation architecture; (3) main/sub bit line and word line structure; and (4) dynamic-type offset sense amplifier.

A 512 Kbit low-voltage NV-SRAM with the size of a conventional SRAM

This paper describes two new circuit techniques for nonvolatile SRAMs with back-up ferroelectric capacitors (NV-SRAMs). These circuits are able to overcome the size and low-voltage-reliability problems faced by the original NV-SRAM. A new 0.25-/spl mu/m-design-rule four-metal-layer NV-SRAM cell occupies 9.7 /spl mu/m/sup 2/, that is the same area as a 0.25-/spl mu/m three-metal-layer SRAM cell. A high-voltage/negative-voltage plate line driver allows a low-voltage-operation NV-SRAM array to improve its nonvolatile retention characteristics. A 512 Kbit test macro has also been designed with only one percent area overhead from a conventional SRAM macro.

A 128-kb FeRAM macro for contact/contactless smart-card microcontrollers

For contact/contactless smart-card applications, a ferroelectric RAM (FeRAM) macro must operate with supply voltages ranging from 2.7 V to 5.5 V, as standardized by ISO, and have endurance of more than 10/sup 8/ write/read cycles and memory size flexible from 32 kb to 128 kb. In addition, for contactless smart card applications, low current consumption is essential. This macro meets these requirements using: (1) 3-metal process capacitor-on-metal/via-stacked-plug (CMVP) memory cell; (2) voltage regulation architecture; (3) main/sub bit line and word line structure; and (4) dynamic-type offset sense amplifier.