Miles A. Copeland

Characterisation and modeling of mismatch in MOS transistors for precision analog design

A characterization methodology is presented that accurately predicts the mismatch in drain current over a wide operating range using a minimum set of measured data. The physical causes of mismatch are discussed in detail for both p- and n-channel devices. Statistical methods are used to develop analytical models that relate the mismatch to the device dimensions. It is shown that these models are valid for small-geometry devices only. Extensive experimental data from a 3-/spl mu/m CMOS process are used to verify the models. The application of the transistor matching studies to the design of a high-performance digital-to-analog converter (DAC) is discussed. A circuit design methodology is presented that highlights the close interaction between the circuit yield and the matching accuracy of devices. It has been possible to achieve a circuit yield of greater than 97% as a result of the knowledge generated regarding the matching behavior of transistors and due to the systematic design approach.

Delta-sigma modulation in fractional-N frequency synthesis

A description is given of a delta-sigma ( Delta - Sigma ) modulation and fractional-N frequency division technique for performing indirect digital frequency synthesis using a phase-locked loop (PLL). The use of Delta - Sigma modulation concepts results in beneficial shaping of the phase noise (jitter) introduced by fractional-N division. The technique has the potential to provide low phase noise, fast settling time, and reduced impact of spurious frequencies when compared with existing fractional-N PLL techniques. >

The modeling, characterization, and design of monolithic inductors for silicon RF IC's

The results of a comprehensive investigation into the characteristics and optimization of inductors fabricated with the top-level metal of a submicron silicon VLSI process are presented. A computer program which extracts a physics-based model of microstrip components that is suitable for circuit (SPICE) simulation has been used to evaluate the effect of variations in metallization, layout geometry, and substrate parameters upon monolithic inductor performance. Three-dimensional (3-D) numerical simulations and experimental measurements of inductors were also used to benchmark the model accuracy. It is shown in this work that low inductor Q is primarily due to the restrictions imposed by the thin interconnect metallization available in most very large scale integration (VLSI) technologies, and that computer optimization of the inductor layout can be used to achieve a 50% improvement in component Q-factor over unoptimized designs.

A 1.9 GHz low-voltage silicon bipolar receiver front-end for wireless personal communications systems

A 1.9 GHz wireless receiver front-end (low-noise preamplifier and mixer) is described that incorporates monolithic microstrip transformers for significant improvements in performance compared to silicon broadband designs. Reactive feedback and coupling elements are used in place of resistors to lower the front-end noise figure through the reduction of resistor thermal noise, and this also allows both circuits to operate at supply voltages below 2 V. These circuits have been fabricated in a production 0.8 /spl mu/m BiCMOS process that has a peak npn transistor transit frequency (f/sub T/) of 11 GHz. At a supply voltage of 1.9 V, the measured mixer input third-order intercept point is +2.3 dBm with a 10.9 dB single-sideband noise figure. Power dissipated by the mixer is less than 5 mW. The low-noise amplifier input intercept is -3 dBm with a 2.8 dB noise figure and 9.5 dB gain. Power dissipation of the preamplifier is less than 4 mW, again from a 1.9 V supply.

A balanced 1.5 GHz voltage controlled oscillator with an integrated LC resonator

A monolithic voltage-controlled oscillator (VCO) is presented for low-power digital radio handsets. This circuit is fabricated in a production 0.8/spl mu/m 11GHz f/sub T/ BiCMOS process. The VCO is based on the common-collector Colpitts circuit in a balanced configuration to provide differential output for direct compatibility with prescaler and double-balanced mixer inputs. The circuit utilizes an integrated LC resonator comprised of coplanar inductors, polysilicon capacitors, and on-chip varactors. The fully-integrated inductors have an unloaded Q of approximately 5 at 2GHz.

An agile ISM band frequency synthesizer with built-in GMSK data modulation

In this paper, a high-resolution fractional-N RF frequency synthesizer is presented which is controlled by a fourth-order digital sigma-delta modulator. The high resolution allows the synthesizer to be digitally modulated directly at RF. A simplified digital filter which makes use of sigma-delta quantized tap coefficients is included which provides built-in GMSK pulse shaping for data transmission. Quantization of the tap coefficients to single-bit values not only simplifies the filter architecture, but the fourth-order digital sigma-delta modulator as well. The synthesizer makes extensive use of custom VLSI, with only a simple off-chip loop filter and VCO required. The synthesizer operates from a single 3-V supply, and has low power consumption. Phase noise levels are less than -90 dBc/Hz at frequency offsets within the loop bandwidth. Spurious components are less than -90 dBc/Hz over a 19.6-MHz tuning range.

A simplified continuous phase modulator technique

A low cost GMSK (Gaussian minimum shift keying) modulation technique is presented. GMSK is chosen as an example although the technique is suitable for any continuous phase constant envelope modulation with discriminator, differential or coherent detection in the targeted receiver. In this technique, a fractional-N synthesizer is used to control the instantaneous frequency and phase of the phase locked synthesizer output. As a result of this approach, no in-phase and quadrature mixer or D/A converters are required. Furthermore, the desired signal can be generated directly at RF with no IF conversion stages. The look-up table to generate the modulation is only one bit wide. /spl Delta/-/spl Sigma/ techniques are used to obtain high accuracy through the long term average of a sequence of the single bits. The narrow band filtering of the transmit data is accomplished in two parts, a precise digital linear phase band-reject part using the one bit stored ROM look-up table and a less precise low pass analog part inherent to the PLL of the synthesizer. >

Design and realization of a digital /spl Delta//spl Sigma/ modulator for fractional-n frequency synthesis

The basic operation of a fractional-n frequency synthesizer has been published, but to date little has been presented on the digital /spl Delta//spl Sigma/ modulators which are required to drive such synthesizers. This paper provides a tutorial overview, which relates digital /spl Delta//spl Sigma/ modulation to other applications of /spl Delta//spl Sigma/ modulation where the literature is more complete. The paper then presents a digital /spl Delta//spl Sigma/ modulator architecture which is economical and efficient and which is practical to realize with commercially available components in comparison with other possible implementations which require extensive custom very large-scale integration (VLSI). A demonstration is made of a 28-b modulator using the architecture presented, which provides a 25-MHz tuning bandwidth and <1-Hz frequency resolution. The modulator is demonstrated in an 800-MHz frequency synthesizer having phase noise of -90 dBC/Hz at a 30-kHz offset.

An oversampling delta-sigma frequency discriminator

A circuit technique for performing oversampled A/D conversion on the phase/frequency information of an angle modulated signal is presented. It is shown that the technique is equivalent to a classic delta-sigma data conversion with instantaneous frequency as the input variable. Details of first and second-order implementations of the technique are presented, and suitability of the technique is discussed for applications such as in the rapidly evolving personal communications field. The most immediate application will be at the IF stage of a receiver where the discriminator input signal is bandlimited by the IF filter, and where sufficient amplification has occurred to provide the input signal levels required by the discriminator. >

An Analysis of the Hysteresis Motor Part III: Parasitic Losses

A major constraint on the performance prediction of a hysteresis machine arises from the parasitic losses associated with the rotor magnetic material. These losses can be high enough to absorb much of the developed torque, particularly for small sizes and large numbers of poles. In this paper the phenomena which cause parasitic losses are examined in detail. Analytical expressions are developed to predict these losses in terms of the air-gap field and the stator current.