Tomio Katata

Highly reliable PVD/ALD/PVD stacked barrier metal structure for 45-nm node copper dual-damascene interconnects

In this paper, we describe highly reliable barrier metal structure for 45nm-node (140nm pitch) high performance copper interconnects. Issues and solutions for utilizing TaN barrier metal by atomic-layer deposition (ALD) process, which is the key technology for scaling down the barrier metal thickness, on low-k ILD materials were investigated. PVD/ALD/PVD stacked barrier metal structure was proposed from the viewpoint of factors affecting reliability such as stress-induced voiding (SiV) and electromigration (EM) endurance, and realized lower wiring resistance than that is attainable with the conventional process. We distinguished the role of each PVD film, and suggest the optimal barrier metal structure to realize highly reliable Cu dual-damascene interconnects.

A Fully Integrated Aluminum Dual Damascene Process Using a New Double Stopper Structure.

A fully integrated aluminum dual damascene process is presented. The process incorporates a double silicon nitride etch stopper structure to achieve better etching control. Use of silicon nitride etch stoppers usually results in increased wire capacitance. However, the new process presented here succeeds in significantly reducing the impact of the silicon nitride stopper layers on wire capacitance by arranging for the stopper layers to be away from the wire corners. The integration of this process with a previously reported aluminum reflow process to obtain an integrated aluminum dual damascene process is described and the results obtained are discussed.

Highly reliable CVD-WSi metal gate electrode for nMOSFETs

In this paper, we first propose an improved chemical vapor deposition (CVD) WSi/sub x/ metal gate suitable for use in nMOSFETs. We studied the relationship between the Si/W ratio of CVD-WSi/sub x/ film and electrical properties of MOSFETs. As a result, it was found that the Si/W ratio strongly affects carrier mobility and the reliability of gate oxide. In the case of higher Si/W ratio, both electron and hole mobility can be improved. For CVD-WSi/sub 3.9/ electrode, electron mobility and hole mobility at 1.2 V of |V/sub g/-V/sub th/| are 331 and 78 cm/sup 2//V/spl middot/s, respectively. These values are almost the same as those for n/sup +/-poly-Si electrode. The improvement of carrier mobility by controlling the Si/W ratio is due to suppression of fluorine contamination in gate oxide. F contamination at the Si/W ratio of 3.9 is found to be less than that at the Si/W ratio of 2.4 from XPS analysis. Workfunction of CVD-WSi/sub 3.9/ gate estimated from C-V measurements is 4.3 eV. In CVD-WSi/sub 3.9/ gate MOSFETs with gate length of 50 nm, a drive current of 636 /spl mu/A//spl mu/m was achieved for off-state leakage current of 35 nA//spl mu/m at power supply voltage of 1.0 V. By using CVD-WSi/sub 3.9/ gate electrode, highly reliable metal gate nMOSFETs can be realized.

Cu dual damascene process for 0.13 um technology generation using self ion sputtering (SIS) with ion reflector

Newly developed self ion sputtering(SIS) system is applied to Cu seed formation for electroplating (EP)-Cu filling. SIS is a bias sputtering using Cu/sup +/ ions generated by self sustained Cu plasma with controlling ion flux to a substrate by an ion reflector. This method can be realized by small modification of long throw sputtering (LTS) configuration. Substrate bias promotes transportation of Cu ions to the bottom of via holes efficiently from Cu plasma, which leads to improve step coverage. However, in the case of only applying substrate bias, uniformity of step coverage across the wafer can not be achieved to the objective value. Ion reflector converges ions on the wafer, especially on the edge of the wafer, then it improves uniformity of step coverage across the wafer. EP-Cu filling of vias of 0.2 um, A/R of 4 can be obtained using this method. Moreover, vias of 0.17 um, A/R of 5 can be completely filled when SIS is applied to barrier metal (TaN) deposition due to drastic improvement of TaN coverage.

High performance Al dual damascene process with elevated double stoppers

An integrated Al dual damascene process which can simultaneously realize smaller interconnect wire resistance variations and reduced wire-to-wire capacitance increase is presented. The main feature of the process is using SiN etch stoppers which are well removed from the corners of the wires. Compared to the conventional damascene structure with SiN etch stoppers directly above and below the wires, the wire-to-wire capacitance increase due to the presence of SiN is reduced by half in the new process. By integrating the process with a newly developed low resistance Al reflow sputter process using a Nb liner, it is confirmed that excellent electrical characteristics are obtained for the dual-damascene wires and vias.

Highly Reliable Metal Gate nMOSFETs by Improved CVD-WSix films with Work Function of 4.3eV

In this paper, we first propose an improved CVD-WSix metal gate suitable for use with nMOSFETs. Work function of CVD-WSi 3.9 gate estimated from C-V measurements was 4.3eV. The nMOSFET using CVD-WSi 3.9 gate electrode showed that Vth variation of L/W=1 μm/10μm nMOSFETs can be suppressed to be lower than 8mV in 22chip. In CVD-WSi 3.9 gate MOSFETs with gate length of 50nm, a drive current of 636μA/μm was achieved for off-state leakage current of 35nA/μm at 1.0V of power supply voltage. By using CVD-WSi 3.9 gate electrode, highly reliable metal gate nMOSFETs can be realized.

Solid phase replacement process for multilevel high-aspect ratio Al fill applications

We present a high aspect ratio Al fill process using solid phase replacement (SPR). In contrast to earlier work in which polysilicon (poly-Si) was used, B-doped amorphous Si (a-Si:B) is used in this work to ensure application in multilevel Al interconnect schemes. a-Si:B is also effective for rapid replacement. We also report, for the fist time, via chain resistance increase and open failure caused by stress-induced voiding during replacement and show that Ti compound formation at the top of the Al film during the replacement anneal is responsible for this void formation. We further provide evidence that SPR can be used as the fill process for multilevel Al dual damascene interconnects if the anneal time and the Si/Ti volume are optimized and a suitable barrier layer is used.