Tomoharu Fujiwara

Nikon EB stepper: its system concept and countermeasures for critical issues

The imaging concept of electron projection lithography (EPL) with silicon stencil reticle is explained. A silicon membrane thickness of 1 - 4 micrometer is suitable for the reticle. A scattering contrast of greater than 99% is expected. Nikon EB steppers dynamic writing strategy of discrete exposure on a sub-field by sub-field basis with deflection control of the electron beam is explained. The basic system configuration of EB stepper is introduced. Examples of error budget for CD variation and Overlay/Stitching are shown. Nikons policy for countermeasures for critical issues such as proximity effect correction, sub-field/complementary stitching and wafer heating influence are explained. For extensibility down to 70 nm and below, both exposure tool and reticle should be improved.

Full-field exposure tools for ArF immersion lithography

Immersion lithography has by far satisfied most expectations regarding its feasibility as the next lithographic technique for the 65-nm node and below. To further advance 193-nm immersion lithography, a means of efficiently controlling water as an immersion fluid and research and development concerning resist processes are necessary. In 2004, Nikon Corporation introduced a 0.85 numerical aperture (NA) 193-nm immersion exposure tool that uses water as the immersion liquid. This engineering evaluation tool (EET) is equipped with a highly efficient temperaturestabilized water nozzle assembly. Selete Inc. in collaboration with Nikon Corporation has been evaluating the performance and various characteristics of the EET while also investigating various photoresist and topcoat processes. We selected three types of standard immersion processes that offered the best performance for our evaluation purposes. A resolution limit of 70-nm half-pitch line-and-space (L/S) patterns has been confirmed. A 0.8-μm depth of focus (DOF) was also verified for an 80-nm half-pitch L/S pattern. In addition, full wafer (WF) critical dimension (CD) uniformity of less than 5 nm (3 sigma) has been demonstrated for a 90-nm half-pitch L/S pattern on a 300-mm wafer (WF). After the implementation of various improvements to both the EET and the topcoat/resist processes, we have achieved a total defect density of 0.23/cm2, and this defect level is low enough for pilot production.

Immersion Lithography Ready for 45 nm Manufacturing and Beyond

Enhanced resolution capability, defined in Rayleighs criterion as: R = (k1*lambda)/NA (1); where R = minimum resolution, lambda = exposure wavelength, and k1 = process dependent factor is the key motivation for the transition to immersion lithography, and the continued push for higher numerical apertures (NA). Regardless of the imaging enhancements made possible by immersion lithography though, this technology would not have been implemented in volume manufacturing if two potential showstoppers identified early on, overlay and defectivity performance, were not successfully overcome. Fortunately, intense collaboration between scanner and track suppliers, resist vendors, and IC manufacturers has yielded significant progress in the critical areas of immersion defectivity and overlay. As a result, immersion lithography is experiencing rapid adoption into mainstream semiconductor manufacturing. Hyper-NA immersion scanners, such as the Nikon NSR-S609B (NA=1.07), began shipping in early 2006 for use in 55 nm production and 45 nm process development. These systems are already being used successfully for 56 nm NAND flash manufacturing. Aggressive industry integration continues, and scanners such as the NSR-S610C (NA=1.30) are fully capable of delivering the critical performance metrics required for 45 nm half-pitch production and beyond. Current areas of industry investigation now focus on the feasibility and practicality of extending immersion lithography to 32 nm applications using new lens and resist materials, as well as exploring alternative immersion fluids to push immersion lithography as far as possible.

Defect studies of resist process for 193nm immersion lithography

193nm immersion lithography is the most promising lithographic technology for the semiconductor device manufacturing of 65nm node and below. The advantage of 193nm immersion lithography is the possibility of wider depth of focus (DOF) and higher resolution through the hyper NA lens design greater than 1.0(1-3). In this paper, we investigated the topcoat material film characteristics and evaluated its performance to determine the chemical properties needed for a practical level. The stage scan speed capability evaluation, which is one of the best available method to test the suppression or generation of small water droplet remains on the topcoat film at high-speed stage scan during immersion exposure, was used. And finally we investigated the defectivity of topcoat process utilizing the Nikon EET. The static and dynamic contact angles of water droplet were investigated to characterize the topcoat material. The tilting sliding and receding angle, the contact angle of water droplet at the dynamic state, were important parameters to characterize the topcoat materials and have good correlation to wafer stage scan speed capability and immersion defect count reduction.

Nikon EB Stepper: the latest development status

The latest development status of EB Stepper is reported. The experimental data include the latest resist image data exposed by 100keV electron beam, mask error factors and dosage margins at several backscattered electron levels, transmission data of continuous membrane reticles, and recommended structures for alignment marks, etc. The basic studies related to system design are also explained, those are the strategy for the management of reticle deformation and the stitching accuracy in overlaid layers, etc. Through these data, the resolution capability down to 50nm technology node is clearly shown and alignment/stitching capability is also described. The requirement to a continuous membrane reticle is indicated from experimental data.

Spacer process and alignment assessment for SADP process

Self Aligned Double Patterning (SADP) is now widely accepted as a viable technology for the further extension of 193nm immersion lithography towards the 22nm /18nm technology nodes. SADP was primary introduced for the manufacturing of flash memory due to its 1D design geometry. However, SADP is now becoming a main stream technology for advanced technology nodes for logic product. SADP results in alignment marks with reduced image contrast after completion of spacer patterning. Consequently there is an elevated risk that the alignment performance of the cut lithography layer on the spacer [1] may be negatively impacted. Initial studies indicate that it may be necessary to consider new mark designs. In this paper, we will evaluate different types of SADP processes with the alignment system of the Nikon S620D and S621D immersion scanner. We will discuss the performances and the differences observed due to the SADP materials. Included in this study is an intensive characterization of the morphology of the spacer after SADP process. We will use for this a 3D-AFM from Insight, and characterize the spacer profile of the spacer. Using a standard AFM microscope, we can characterize the surface roughness in the inner and the outer part of the wafer. The self aligned spacer process results in asymmetric spacers. Two types of surface (inside and outside) of the spacer are formed. The impact of this asymmetry is also assessed. The roughness difference, between the two parts, will play an important roll in the alignment contrast.

Immersion defectivity study with volume production immersion lithography tool for 45 nm node and below

Volume production of 45nm node devices utilizing Nikons S610C immersion lithography tool has started. Important to the success in achieving high-yields in volume production with immersion lithography has been defectivity reduction. In this study we evaluate several methods of defectivity reduction. The tools used in our defectivity analysis included a dedicated immersion cluster tools consisting of a Nikon S610C, a volume production immersion exposure tool with NA of 1.3, and a resist coater-developer LITHIUS i+ from TEL. In our initial procedure we evaluated defectivity behavior by comparing on a topcoat-less resist process to a conventional topcoat process. Because of its simplicity the topcoatless resist shows lower defect levels than the topcoat process. In a second study we evaluated the defect reduction by introducing the TEL bevel rinse and pre-immersion bevel cleaning techniques. This technique was shown to successfully reduce the defect levels by reducing the particles at the wafer bevel region. For the third defect reduction method, two types of tool cleaning processes are shown. Finally, we discuss the overall defectivity behavior at the 45nm node. To facilitate an understanding of the root cause of the defects, defect source analysis (DSA) was applied to separate the defects into three classes according to the source of defects. DSA analysis revealed that more than 99% of defects relate to material and process, and less than 1% of the defects relate to the exposure tool. Material and process optimization by collaborative work between exposure tool vendors, track vendors and material vendors is a key for success of 45nm node device manufacturing.

Defect-aware process margin for chemo-epitaxial directed self-assembly lithography using simulation method based on self-consistent field theory

We proposed a new concept of “defect-aware process margin.” Defect-aware process margin was evaluated by investigating the energy difference between the free-energy of the most stable state and that of the first metastable state. The energy difference is strongly related to the defect density in DSA process. As a result of our rigorous simulations, the process margin of the pinning layer width was found to be: (1) worse when the pinning layer affinity is too large, (2) better when the background affinity has the opposite sign of the pinning layer affinity, and (3) better when the top of the background layer is higher than that of the pinning layer by 0.1L0.

Control and reduction of immersion defectivity for yield enhancement at high volume production

Volume device manufacturing using immersion lithography is widely accepted as the solution for patterning IC features below 40 nm half pitch. In order to ensure high yield and steady productivity tight control of defectivity is essential. A major source of defects and tool contamination is the particles introduced by incoming wafers. Particles can be categorized in two groups: particles attached to wafer surface or residues on the wafer edge. Surface or edge peeling of topcoats can also be a source of particle. Adhesion force between topcoat or topcoat-less (TC-less) resist and wafer is one of the most important parameter for particle reduction. Peeling test results proved that TC-less resist has better adhesion performance than topcoat. One of the most commonly used adhesion promoting material is hexamethyldisilazane (HMDS). Application condition of this material is an important factor in preventing wafer edge and surface topcoat peeling. Studies have shown lower temperature and longer application of HMDS shows better adhesion result. Maintaining a clean wafer surface is also a very important factor for particle reduction. Pre-rinse, which can rinse off particles before exposure, was evaluated and the efficiency was confirmed. Edge particles are more effectively reduced by pre-rinse, because weakly attached topcoat and wafer edge residues were effectively removed by pre-rinse. For further particle reduction, edge residue reduction and cut line roughness improvement were evaluated and their effectiveness was confirmed. Lower cut position achieved improved particle counts on both topcoat and TC-less resist; more frequent contact between water and cut-line can weaken the adhesion and consequently peel off topcoat or TC-less resist. Finally the relationship between defectivity and hydrophobicity is analyzed, high Receding Contact Angle (RCA) showed better defectivity result. Topcoat and TC-less process is compared for each defectivity reduction methodology and for each category TC-less process always showed lower defectivity level and less sensitivity to process conditions, indicating that TC-less process is safer and more robust than topcoat process.

Immersion defectivity study with volume production immersion lithography tool

ArF immersion lithography has become accepted as the critical layer patterning solution for lithography going forward. Volume production of 55 nm devices using immersion lithography has begun. One of the key issues for the success of volume production immersion lithography is the control of immersion defectivity. Because the defectivity is influenced by the exposure tool, track, materials, and the wafer environment, a broad range of analysis and optimization is needed to minimize defect levels. Defect tests were performed using a dedicated immersion cluster consisting of a volume production immersion exposure tool, Nikon NSR-S609B, having NA of 1.07, and a resist coater-developer, TEL LITHIUS i+. Miniaturization of feature size by immersion lithography requires higher sensitivity defect inspection. In this paper, first we demonstrate the high sensitivity defect measurement using a next generation wafer inspection system, KLA-Tencor 2800 and Surfscan SP2, on both patterned and non-patterned wafers. Long-term defect stability is very important from the viewpoint of device mass production. Secondly, we present long-term defectivity data using a topcoat-less process. For tool and process qualification, a simple monitor method is required. Simple, non-pattern immersion scanned wafer measurement has been proposed elsewhere, but the correlation between such a non-pattern defect and pattern defect must be confirmed. In this paper, using a topcoat process, the correlation between topcoat defects and pattern defects is analyzed using the defect source analysis (DSA) method. In case of accidental tool contamination, a cleaning process should be established. Liquid cleaning is suitable because it can be easily introduced through the immersion nozzle. An in-situ tool cleaning method is introduced. A broad range of optimization of tools, materials, and processes provide convincing evidence that immersion lithography is ready for volume production chip manufacturing.