Tomohiro Tamaki

Optimization of on -State and Switching Performances for 15–20-kV 4H-SiC IGBTs

The 4H-SiC p-channel IGBTs designed to block 15 and 20 kV are optimized for minimum loss (on-state plus switching power) by adjusting the parameters of the JFET region, drift layer, and buffer layer, using 2-D MEDICI simulations. Switching loss exhibits a strong dependence on buffer layer thickness, doping, and lifetime due to their influence on the current tail. In contrast, drift layer lifetime has little effect on the crossover frequency at which the MOSFET and IGBT have equal loss.

Numerical Study of the Turnoff Behavior of High-Voltage 4H-SiC IGBTs

The turnoff behavior of high-voltage 4H-SiC p-channel insulated gate bipolar transistors is investigated by 2-D numerical simulations. Minority carrier lifetime in the nonpunch-through buffer layer is found to be the major factor determining switching loss.

Power MOSFETs, IGBTs, and thyristors in SiC: Optimization, experimental results, and theoretical performance

In this paper we present recent experimental results on SiC MOSFETs, IGBTs, and thyristors, and propose a consistent methodology for comparing unipolar and bipolar power devices as a function of blocking voltage and switching frequency.

A 69-mΩ 600-V-Class Hybrid JFET

A hybrid silicon-carbide junction-gate field-effect transistor (HJT: hybrid JFET) is proposed. The HJT consists of a silicon-carbide (SiC) normally-on vertical JFET and a low-voltage normally-off silicon metal-oxide-semiconductor field-effect transistor (Si-MOS: silicon MOSFET). These two devices are connected by bonding wire as a cascode circuit [1] and packaged in a TO-3P split-lead-frame package with the same pin arrangement as conventional silicon power devices, which can thus be easily replaced by the proposed HJT. The vertical JFET has a steep-junction deep-trench structure in its channel region. This structure gives a low on-state resistance of under 60 mΩ and breakdown voltage of over 600 V with the die size of 6.25 mm2. Since the deep-trench structure also lowers the cutoff voltage of the JFET, required minimum breakdown voltage of the Si-MOS is reduced and on-state resistance of the Si-MOS is lowered. The HJT demonstrated on-state resistance of 69 mΩ and breakdown voltage of 783 V. These results indicate that the proposed HJT is a strong candidate for low-resistance high-power switching devices.

On-State and Switching Performance Comparison of A 600 V-Class Hybrid SiC JFET and Si Superjunction MOSFETs

We compare the on-state and switching performance of a 600 V-class Hybrid SiC junction field effect transistor (HJT) and Si superjunction MOSFETs (SJ-MOSs), both of which are packaged in TO-3P full-mold package, as a function of operating frequency. The maximum load current is limited by the package power dissipation rating determined by the maximum junction temperature. Since the HJT is composed of a SiC JFET and a low voltage Si MOSFET, the allowable maximum junction temperature of the HJT is the same as that of SJ-MOSFETs, namely 150 °C. The experimental results show that the maximum operating current of the HJT is comparable to that of SJ-MOSs, but the EMI noise of the HJT is much suppressed due to lower dV/dt.