Satoru Akiyama

Low-V t small-offset gated preamplifier for sub-1V gigabit DRAM arrays

A sensing scheme with temporary activation of a low-Vt gated preamplifier (LGA) achieves fast sensing, fast local I/O driving and low-leakage operation simultaneously even for low-voltage mid-point sensing. The features are verified with a 70nm 128Mb DRAM core that demonstrates 16.4ns row access (tRCD) and 14.3ns read access (tAA) at an array voltage of 0.9V. The LGA is promising for future sub-1V gigabit DRAMs because it reduces variation in threshold voltage (Vt) of MOSFETs and in the offset voltage of sense amplifiers.

A fully logic-process-compatible, 3-transistor, SESO-memory cell featuring 0.1-FIT/Mb soft error, 100-MHz random cycle, and 100-ms retention

A 1-kb memory-cell array composed of single-electron shut-off (SESO) cells was fabricated with the 90-nm logic process for the first time. It features a 0.1-FIT/Mb soft error, 100-MHz random cycle, and 100-ms retention. In addition to a logic-compatible cell structure and a write-data caching scheme, a backup latch circuit with SESO transistors for logic application was also proposed.

Concordant memory design using statistical integration for the billions-transistor era

An embedded DRAM macro in a logic compatible 90nm CMOS process is designed with low-noise core architecture and high-accuracy post-fabrication tuning. With a 5fF/cell capacitance, a 61% improvement of sensing accuracy enables 322MHz random-cycle operation and reduces data retention power to 60 /spl mu/W.

Long-Retention-Time, High-Speed DRAM Array with 12-F2 Twin Cell for Sub 1-V Operation

A DRAM-cell array with 12-F 2 twin cell was developed and evaluated in terms of speed, retention time, and low-voltage operation. The write and read-out times of the twin-cell array are shorter than those of a single-cell array by 70% and 40% respectively, because of parallel writing and reading of half charge to and from two memory cells. According to measured retention characteristics of the single cells, the twin-cell array improves retention time by 20% compared with the single-cell array at 1V and keeps the retention time of the single-cell array at 0.4 V. Furthermore, the cell accepts the plate-driven scheme without the need of a dummy cell, lowering the necessary word-line voltage by 0.4 V.

Controllability of switching speed and loss for SiC JFET/Si MOSFET cascode with external gate resistor

The SiC JFET/Si MOSFET cascode is an attractive alternative to conventional Si MOSFETs or IGBTs due to its low on-resistance and good switching performance. However, dv/dt control without increased switching loss is difficult when using a conventional gate resistor or capacitor for the MOSFET. In this paper, a dv/dt and switching loss control method that ensures a good switching performance for the cascode with an external gate resistor for JFET, as well as for MOSFET, is presented.

Study on low-loss gate drive circuit for high efficiency server power supply using normally-off SiC-JFET

We investigated how to reduce the energy loss of server power supplies equipped with vertical-trench normally-off Silicon Carbide junction-gate field-effect transistors (SiC-JFETs). High-speed driving circuits consisting of a speed-up capacitor with separated source terminal and timing adjust circuits to ensure a dead time margin are proposed. Applying the developed normally-off SiC-JFETs and the proposed gate driver to PFC circuits and DC/AC circuits resulted in, an increase of server power supply efficiency to 95.10%.

Lateral Solid-Phase Recrystallization from the Crystal Seed Selectively Formed by Excimer Laser Annealing in Ge-Ion-Implanted Amorphous Silicon Films

A new recrystallization method improving the electrical properties of polycrystalline silicon (poly-Si) thin-film transistors (TFTs) and reducing the fluctuation of the electrical characteristics among them is proposed. It can be realized by the amorphization of poly-Si films through Ge-ion implantation, the crystallization of the drain region, which functions as a crystal seed in the subsequent process, through excimer laser annealing (ELA), and lateral solid-phase recrystallization (LSPR) from the drain to the source along the channel through furnace annealing. In this study, basic experiments are performed to determine the optimum condition of ELA for the formation of the crystal seed with good crystallinty and to investigate the aspect of LSPR growth from the seed.

600-V 27-mΩ normally off SiC junction field effect transistors for high-efficiency power supply

Normally-off SiC junction field effect transistors (JFETs) with high blocking voltage and low gate leakage current were developed by localized current-path doping (LCD). Numerical simulation of electric field revealed that LCD effectively decreases the on-resistance of SiC JFETs without degrading blocking voltage. On the basis of the obtained simulation results, 600-V 27-mΩ normally off SiC JFETs were fabricated by LDC. The gate leakage current of the fabricated JFETs was suppressed by surface oxynitridation. By applying in a server power supply, we found that these improved JFETs decreased power loss due to FETs by 66%.

A 69-mΩ 600-V-Class Hybrid JFET

A hybrid silicon-carbide junction-gate field-effect transistor (HJT: hybrid JFET) is proposed. The HJT consists of a silicon-carbide (SiC) normally-on vertical JFET and a low-voltage normally-off silicon metal-oxide-semiconductor field-effect transistor (Si-MOS: silicon MOSFET). These two devices are connected by bonding wire as a cascode circuit [1] and packaged in a TO-3P split-lead-frame package with the same pin arrangement as conventional silicon power devices, which can thus be easily replaced by the proposed HJT. The vertical JFET has a steep-junction deep-trench structure in its channel region. This structure gives a low on-state resistance of under 60 mΩ and breakdown voltage of over 600 V with the die size of 6.25 mm2. Since the deep-trench structure also lowers the cutoff voltage of the JFET, required minimum breakdown voltage of the Si-MOS is reduced and on-state resistance of the Si-MOS is lowered. The HJT demonstrated on-state resistance of 69 mΩ and breakdown voltage of 783 V. These results indicate that the proposed HJT is a strong candidate for low-resistance high-power switching devices.

0.5-V Low-

A novel low-VT CMOS preamplifier was developed for low-power and high-speed gigabit DRAM arrays. The sensing time of a sense amplifier (SA) with the proposed preamplifier and its activation schemes at a data-line voltage of 0.5 V was 6 ns, which is 62% shorter than that of an SA using a conventional preamplifier. By activating the proposed preamplifier temporarily during the write cycle, the writing time was 16.3 ns, which is 72% shorter than the case without activation of the proposed preamplifier, and this time is short enough to apply a DRAM array using the proposed preamplifier to 1.6-Gbit/s/pin DDR3 SDRAM. The operating current of the memory array and its peripheral circuit including the proposed preamplifier was reduced by 12% by reducing the data-line voltage from 0.8 to 0.5 V.