Toshihiro Iizuka

Low temperature deposition of (Ba, Sr)TiO3 films by electron cyclotron resonance plasma chemical vapor deposition

(Ba, Sr)TiO 3 films deposited by electron cyclotron resonance plasma chemical vapor deposition at 450°C and 500°C are investigated. The crystallinity, evaluated by X-ray diffraction and by measuring grain size, and electrical properties of films were evaluated for changes in deposition temperature, deposition rate, and Ba content, without a post-deposition annealing. Slower deposition rates as well as higher deposition temperatures were found to improve film crystallinity. Evaluation of electrical properties and film crystallinity revealed that the optimum Ba content of a film deposited at 500°C was 0.4. A 27nm thick film deposited on a Pt substrate at 500°C and at 1.1 nm/min with a Ba content of 0.4 exhibited a SiO 2 equivalent thickness of 0.65 nm and a leakage current density of 4.6 x 10 -7 A/cm 2 at 1V. The film composition was found to be sufficiently uniform throughout, i.e., from the top to the side of the films on a stacked bottom electrode.

Plasma CVD of (BaSr)TiO3 Dielectrics for Gigabit DRAM Capacitors

Electron cyclotron resonance (ECR) plasma chemical vapor deposition (CVD) of (BaSr)TiO3 dielectrics is reviewed. The oxygen plasma lowered the crystallization temperature and carbon contamination. (BaSr)TiO3 CVD process was developed under conditions of relatively low deposition rate of 1.1 nm/min and a relatively low deposition temperature of 550°C. Utilizing this process, we developed a gigabit dynamic random access memory (DRAM) capacitor technology involving the preparation of a thin (BaSr)TiO3 capacitor dielectric over a RuO2/Ru storage node contacting a TiN/TiSiX/poly-Si plug. The ECR plasma CVD enabled uniform deposition of gigabit-DRAM-quality (BaSr)TiO3 films on the electrode sidewalls. The storage node contact improved in endurance against oxidation, by fabricating the buried-in TiN/TiSiX plug (TiN-capped plug) under the RuO2/Ru storage node. (BaSr)TiO3 films with a small equivalent SiO2 thickness of 0.38 nm and a leakage current density of 8.5×10−7 A/cm2 at an applied voltage of 1.0 V, were obtained without any further annealing process. An equivalent SiO2 thickness of 0.40 nm on the RuO2 sidewall was also achieved. It is concluded that this technology has reached the requirements for gigabit DRAM capacitors.

Low Temperature Recovery of Ru/(Ba, Sr)TiO3/Ru Capacitors Degraded by Forming Gas Annealing

A low temperature N2 post-annealing process was proposed to improve the degradation of Ru/(Ba, Sr)TiO3/Ru capacitors due to forming gas annealing. After N2 post-annealing at 300°C, the leakage current degraded by forming gas annealing was completely recovered to the initial level without affecting the SiO2 equivalent thickness of 0.51 nm. No degradation of the subthreshold characteristics of n-channel metal-oxide-semiconductor field effect transistors and N+P junction leakage current by the post-annealing was also confirmed. The Ru/(Ba, Sr)TiO3/Ru capacitor technology with this post-annealing process is suitable for dynamic random access memories in 0.13 µm generation and beyond.