Shozo Nishimoto

A low voltage operating flash memory cell with high coupling ratio using horned floating gate with fine HSG

We achieved a novel low voltage operating flash memory cell with high coupling ratio of 0.9 which has a horned floating gate (FG) with fine HSG. The increase in the coupling ratio can reduce programming and erasing operation voltages by a maximum 4 V. Enlargement of the FG surface area by extending in the vertical direction enables the high coupling ratio without increasing cell area. In addition, the increase in the coupling ratio is significant when cell size is shrunk. We consider the horned FG cell with HSG as the most promising candidate for the flash memory cell in 0.25 and 0.18 /spl mu/m design rules.

Low temperature deposition of (Ba, Sr)TiO3 films by electron cyclotron resonance plasma chemical vapor deposition

(Ba, Sr)TiO 3 films deposited by electron cyclotron resonance plasma chemical vapor deposition at 450°C and 500°C are investigated. The crystallinity, evaluated by X-ray diffraction and by measuring grain size, and electrical properties of films were evaluated for changes in deposition temperature, deposition rate, and Ba content, without a post-deposition annealing. Slower deposition rates as well as higher deposition temperatures were found to improve film crystallinity. Evaluation of electrical properties and film crystallinity revealed that the optimum Ba content of a film deposited at 500°C was 0.4. A 27nm thick film deposited on a Pt substrate at 500°C and at 1.1 nm/min with a Ba content of 0.4 exhibited a SiO 2 equivalent thickness of 0.65 nm and a leakage current density of 4.6 x 10 -7 A/cm 2 at 1V. The film composition was found to be sufficiently uniform throughout, i.e., from the top to the side of the films on a stacked bottom electrode.

Plasma CVD of (BaSr)TiO3 Dielectrics for Gigabit DRAM Capacitors

Electron cyclotron resonance (ECR) plasma chemical vapor deposition (CVD) of (BaSr)TiO3 dielectrics is reviewed. The oxygen plasma lowered the crystallization temperature and carbon contamination. (BaSr)TiO3 CVD process was developed under conditions of relatively low deposition rate of 1.1 nm/min and a relatively low deposition temperature of 550°C. Utilizing this process, we developed a gigabit dynamic random access memory (DRAM) capacitor technology involving the preparation of a thin (BaSr)TiO3 capacitor dielectric over a RuO2/Ru storage node contacting a TiN/TiSiX/poly-Si plug. The ECR plasma CVD enabled uniform deposition of gigabit-DRAM-quality (BaSr)TiO3 films on the electrode sidewalls. The storage node contact improved in endurance against oxidation, by fabricating the buried-in TiN/TiSiX plug (TiN-capped plug) under the RuO2/Ru storage node. (BaSr)TiO3 films with a small equivalent SiO2 thickness of 0.38 nm and a leakage current density of 8.5×10−7 A/cm2 at an applied voltage of 1.0 V, were obtained without any further annealing process. An equivalent SiO2 thickness of 0.40 nm on the RuO2 sidewall was also achieved. It is concluded that this technology has reached the requirements for gigabit DRAM capacitors.

Effect of Low-Dose Ion Implantation on the Stress of Low-Pressure Chemical Vapor Deposited Silicon Nitride Films

We investigated the effect of reducing stress in low-pressure chemical vapor deposited (LPCVD)-Si3N4 films by a low-dose ion implantation of P, Ar and As. The tensile stress of the Si3N4 films was eliminated by implanting these ions in the middle of the films in doses as low as 3×1013 to 1.2×1014 cm-2. After annealing, although the stress of the implanted nitride films recovers partially, its value still does not reach that of the unimplanted films. The influence of implantation on the local oxidation of silicon (LOCOS) profile and the device characteristics is negligible.

Novel salicide technology using Ti hydrogenation for 0.1 /spl mu/m CMOS

A novel titanium self-aligned silicide (Ti salicide) process has been developed that uses in situ rapid thermal hydrogenation (RTH) of the Ti prior to rapid thermal annealing (RTA) to achieve 0.1-/spl mu/m CMOS. The in situ RTH enhances the silicidation reaction and reduces the nitridation reaction of the Ti. A low C54-TiSi/sub 2/ sheet resistance of 11.7 /spl Omega///spl square/ was obtained at a 0.1-/spl mu/m line width with 15-nm-thick deposited Ti.

Yield enhancement effects of boosted dual word-line (BDWL) scheme for high density DRAMs

This paper describes the yield enhancement effects of a boosted dual word-line (BDWL) scheme for the first Al wiring in high density DRAMs, with a defect density model and a yield model used for comparison with that of the commonly used word-shunt (WS) scheme. Additionally, the yield of first Al wiring with a step height between memory cell array and peripheral circuit regions is also estimated. The yield estimation demonstrated that the yield enhancement effect of the wide first Al wiring for the BDWL scheme was comparable with or surpassed that of the redundancy for the WS scheme yield, when the first Al wiring pitch over the memory cell array or a BDWL scheme was over 4 times wider than that of the WS scheme. The yield estimation with step height indicated that the first Al wiring yield of the BDWL scheme with the step height exceeded that of the WS scheme with the step height of zero, even if using some global planarization technology.