Hirohisa Iizuka

Electrically alterable avalanche-injection-type MOS READ-ONLY memory with stacked-gate structure

Design theory and experimental results of the WRITE and ERASE properties of a rewritable and nonvolatile avalanche-injection-type memory are reported. The memory transistor has the stacked-gate structure of a floating gate and a control gate. The threshold-voltage shift of the transistor due to injected charge is controlled by applied potential on the control gate which reduces the avalanche breakdown voltage of the drain junction and accelerates electron injection into the floating gate. The writing time is about 20 µs for a single transistor and is less than 5 s for a fully decoded 2048-bit memory with appropriate duty cycles of programming pulses. Erasure of the memory is accomplished either by ultraviolet light irradiation onto the floating gate or by electric field emission of electrons from the floating gate to the control gate. Electrical erasing is theoretically analyzed and successfully compared with experimental results on the 2K bit memory. Memory retention is also investigated and a charge-escaping model is proposed.

A new write/erase method to improve the read disturb characteristics based on the decay phenomena of stress leakage current for flash memories

This paper describes a new write/erase method for flash memory to improve the read disturb characteristics by means of drastically reducing the stress leakage current in the tunnel oxide. This new write/erase operation method is based on the newly discovered three decay characteristics of the stress leakage current. The features of the proposed write/erase method are as follows: 1) the polarity of the additional pulse after applying write/erase pulse is the same as that of the control gate voltage in the read operation; 2) the voltage of the additional pulse is higher than that of a control gate in a read operation, and lower than that of a control gate in a write operation; and 3) an additional pulse is applied to the control gate just after a completion of the write/erase operation. With the proposed write/erase method, the degradation of the read disturb life time after 10/sup 6/ write/erase cycles can be drastically reduced by 50% in comparison with the conventional bipolarity write/erase method used for NAND type flash memory. Furthermore, the degradation can he drastically reduced by 90% in comparison with the conventional unipolarity write/erase method fur NOR-, AND-, and DINOR-type flash memory. This proposed write/erase operation method has superior potential for applications to 256 Mb flash memories and beyond.

A novel gate-offset NAND cell (GOC-NAND) technology suitable for high-density and low-voltage-operation flash memories

This paper describes a novel scaled and low-voltage-operation NAND EEPROM technology with a G_ate-O_ffset NAND C_ell (GOC-NAND), which is free from program disturbance in a self-boosted program. In GOC-NAND, novel source/drain engineering is introduced for the first time. The program disturbance is decreased by two decades of magnitude in 0.1 /spl mu/m generation, without area penalty and additional process steps. Furthermore, the program disturbance is not increased by scaling and low voltage operation. Therefore, GOC-NAND is indispensable technology for gigabit-scaled NAND EEPROMs.

A novel surface-oxidized barrier-SiN cell technology to improve endurance and read-disturb characteristics for gigabit NAND flash memories

This paper describes a novel surface-oxidized barrier-SiN cell technology to effect a tenfold improvement in endurance and read disturb characteristics. In conventional memory cells, degradation of tunnel oxides due to barrier-SiN films for Self-Aligned Contact (SAC) limits the scaling of memory cells. The proposed technology overcomes this problem by an additional oxidation process subsequent to barrier-SiN deposition to reduce hydrogen in both SiN film and tunnel oxide. 0.18 /spl mu/m-rule NAND cells fabricated by the proposed technology demonstrate a tenfold improvement in allowable program/erase cycles and read disturb lifetime without any deterioration of other cell properties.

An Advanced NAND-Structure Cell Technology for Reliable 3.3 V 64 Mb Electrically Erasable and Programmable Read Only Memories (EEPROMs)

An extremely small NAND-structure cell of 1.13 µm2 per bit, 80% of the smallest Flash memory cell reported so far [H. Kume et al.: IEEE Tech. Dig. IEDM (1992) p. 991], has been developed in 0.4 µm technology. The chip size of a 64 Mb NAND electrically erasable and programmable read only memory (EEPROM) using this cell is estimated to be 120 mm2, which is 60% that of a 64 Mb DRAM. In order to realize the small cell size, a 0.8 µm field isolation is used. A negative bias of -0.5 V to the P-well of the memory cell is applied during writing. In addition, a bit-by-bit intelligent writing technology allows a 3.3 V data sensing scheme which can suppress read disturb to 1/1000 in comparison with the conventional 5 V scheme. As a result, it is expected that with this technology, 106 write and erase cycles can be achieved and that the tunnel oxide can be scaled down from 10 nm to 8 nm.

A new write/erase method for the reduction of the stress-induced leakage current based on the deactivation of step tunneling sites for flash memories

This paper describes a new write/erase method to improve the read disturb characteristics by means of drastically reducing the stress-induced leakage current in the tunnel oxide. With the proposed write/erase method, the degradation of the read disturb life time after 10/sup 6/ write/erase cycles can be drastically reduced to 50% in comparison with the conventional bipolarity write/erase method. The features of the proposed write/erase method are as follows: (1) applying an additional pulse to the control gate just after completion of the write/erase operation; (2) the voltage of the additional pulse is higher than that of the control gate in a read operation, and lower than that of the control gate in a write operation; and (3) the polarity of the voltage is the same as that of the control gate voltage in the read operation. This proposed write/erase method is based on the deactivation mechanism of the leakage current, which is discussed in detail in this paper.<<ETX>>